JAJSFV9D September   2015  – July 2018 CC1310

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram – RSM Package
    2. 4.2 Signal Descriptions – RSM Package
    3. 4.3 Pin Diagram – RHB Package
    4. 4.4 Signal Descriptions – RHB Package
    5. 4.5 Pin Diagram – RGZ Package
    6. 4.6 Signal Descriptions – RGZ Package
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
    5. 5.5  RF Characteristics
    6. 5.6  Receive (RX) Parameters, 861 MHz to 1054 MHz
    7. 5.7  Receive (RX) Parameters, 431 MHz to 527 MHz
    8. 5.8  Transmit (TX) Parameters, 861 MHz to 1054 MHz
    9. 5.9  Transmit (TX) Parameters, 431 MHz to 527 MHz
    10. 5.10 PLL Parameters
    11. 5.11 ADC Characteristics
    12. 5.12 Temperature Sensor
    13. 5.13 Battery Monitor
    14. 5.14 Continuous Time Comparator
    15. 5.15 Low-Power Clocked Comparator
    16. 5.16 Programmable Current Source
    17. 5.17 DC Characteristics
    18. 5.18 Thermal Characteristics
    19. 5.19 Timing and Switching Characteristics
      1. 5.19.1 Reset Timing
        1. Table 5-1 Reset Timing
      2. 5.19.2 Wakeup Timing
        1. Table 5-2 Wakeup Timing
      3. 5.19.3 Clock Specifications
        1. Table 5-3 24-MHz Crystal Oscillator (XOSC_HF)
        2. Table 5-4 32.768-kHz Crystal Oscillator (XOSC_LF)
        3. Table 5-5 48-MHz RC Oscillator (RCOSC_HF)
        4. Table 5-6 32-kHz RC Oscillator (RCOSC_LF)
      4. 5.19.4 Flash Memory Characteristics
        1. Table 5-7 Flash Memory Characteristics
      5. 5.19.5 Synchronous Serial Interface (SSI) Characteristics
        1. Table 5-8 Synchronous Serial Interface (SSI) Characteristics
    20. 5.20 Typical Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Main CPU
    3. 6.3  RF Core
    4. 6.4  Sensor Controller
    5. 6.5  Memory
    6. 6.6  Debug
    7. 6.7  Power Management
    8. 6.8  Clock Systems
    9. 6.9  General Peripherals and Modules
    10. 6.10 Voltage Supply Domains
    11. 6.11 System Architecture
  7. 7Application, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 TI Design or Reference Design
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1  デバイスの項目表記
    2. 8.2  ツールとソフトウェア
    3. 8.3  ドキュメントのサポート
    4. 8.4  テキサス・インスツルメンツのローパワーRF Webサイト
    5. 8.5  追加情報
    6. 8.6  コミュニティ・リソース
    7. 8.7  商標
    8. 8.8  静電気放電に関する注意事項
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージ情報

5.11 ADC Characteristics

Tc = 25°C, VDDS = 3.0 V, DC/DC disabled. Input voltage scaling enabled, unless otherwise noted.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range 0 VDDS V
Resolution 12 Bits
Sample rate 200 ksamples/s
Offset Internal 4.3-V equivalent reference(2) 2.1 LSB
Gain error Internal 4.3-V equivalent reference(2) –0.14 LSB
DNL(3) Differential nonlinearity >–1 LSB
INL(4) Integral nonlinearity ±2 LSB
ENOB Effective number of bits Internal 4.3-V equivalent reference(2), 200 ksamples/s,
9.6-kHz input tone		 10.0 Bits
VDDS as reference, 200 ksamples/s, 9.6-kHz input tone 10.2
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksamples/s, 300-Hz input tone		 11.1
THD Total harmonic distortion Internal 4.3-V equivalent reference(2), 200 ksamples/s,
9.6-kHz input tone		 –65 dB
VDDS as reference, 200 ksamples/s, 9.6-kHz input tone –72
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksamples/s, 300-Hz input tone		 –75
SINAD
and
SNDR		 Signal-to-noise and distortion ratio Internal 4.3-V equivalent reference(2), 200 ksamples/s,
9.6-kHz input tone		 62 dB
VDDS as reference, 200 ksamples/s, 9.6-kHz input tone 63
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksamples/s, 300-Hz input tone		 69
SFDR Spurious-free dynamic range Internal 4.3-V equivalent reference(2), 200 ksamples/s,
9.6-kHz input tone		 74 dB
VDDS as reference, 200 ksamples/s, 9.6-kHz input tone 75
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksamples/s, 300-Hz input tone		 75
Conversion time Including sampling time 5 µs
Current consumption Internal 4.3-V equivalent reference(2) 0.66 mA
Current consumption VDDS as reference 0.75 mA
Reference voltage Equivalent fixed internal reference(voltage scaling enabled) (2)
For best accuracy, the ADC conversion should be initiated through the TI-RTOS API in order to include the gain/offset compensation factors stored in FCFG1.		 4.3 V
Reference voltage Fixed internal reference (input voltage scaling disabled). (2)
For best accuracy, the ADC conversion should be initiated through the TI-RTOS API in order to include the gain/offset compensation factors stored in FCFG1. This value is derived from the scaled value (4.3 V) as follows:
Vref = 4.3 V × 1408 / 4095		 1.48 V
Reference voltage VDDS as reference (Also known as RELATIVE) (input voltage scaling enabled) VDDS V
Reference voltage VDDS as reference (Also known as RELATIVE) (input voltage scaling disabled) VDDS / 2.82 V
Input Impedance 200 ksamples/s, voltage scaling enabled. Capacitive input, input impedance depends on sampling frequency and sampling time >1 MΩ
(1) Using IEEE Std 1241™ 2010 for terminology and test methods.
(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V. Applied voltage must be within the absolute maximum ratings (see Section 5.1) at all times.
(3) No missing codes. Positive DNL typically varies from 0.3 to 1.7, depending on the device (see Figure 5-7).
(4) For a typical example, see Figure 5-6.