JAJSFW0F July 2018 – February 2021 CC1352P
PRODUCTION DATA
PIN | I/O | TYPE | DESCRIPTION | |
---|---|---|---|---|
NAME | NO. | |||
DCDC_SW | 33 | — | Power | Output from internal DC/DC converter(1) |
DCOUPL | 23 | — | Power | For decoupling of internal 1.27 V regulated digital-supply (2) |
DIO_5 | 10 | I/O | Digital | GPIO, high-drive capability |
DIO_6 | 11 | I/O | Digital | GPIO, high-drive capability |
DIO_7 | 12 | I/O | Digital | GPIO, high-drive capability |
DIO_8 | 14 | I/O | Digital | GPIO |
DIO_9 | 15 | I/O | Digital | GPIO |
DIO_10 | 16 | I/O | Digital | GPIO |
DIO_11 | 17 | I/O | Digital | GPIO |
DIO_12 | 18 | I/O | Digital | GPIO |
DIO_13 | 19 | I/O | Digital | GPIO |
DIO_14 | 20 | I/O | Digital | GPIO |
DIO_15 | 21 | I/O | Digital | GPIO |
DIO_16 | 26 | I/O | Digital | GPIO, JTAG_TDO, high-drive capability |
DIO_17 | 27 | I/O | Digital | GPIO, JTAG_TDI, high-drive capability |
DIO_18 | 28 | I/O | Digital | GPIO |
DIO_19 | 29 | I/O | Digital | GPIO |
DIO_20 | 30 | I/O | Digital | GPIO |
DIO_21 | 31 | I/O | Digital | GPIO |
DIO_22 | 32 | I/O | Digital | GPIO |
DIO_23 | 36 | I/O | Digital or Analog | GPIO, analog capability |
DIO_24 | 37 | I/O | Digital or Analog | GPIO, analog capability |
DIO_25 | 38 | I/O | Digital or Analog | GPIO, analog capability |
DIO_26 | 39 | I/O | Digital or Analog | GPIO, analog capability |
DIO_27 | 40 | I/O | Digital or Analog | GPIO, analog capability |
DIO_28 | 41 | I/O | Digital or Analog | GPIO, analog capability |
DIO_29 | 42 | I/O | Digital or Analog | GPIO, analog capability |
DIO_30 | 43 | I/O | Digital or Analog | GPIO, analog capability |
EGP | — | — | GND | Ground – exposed ground pad(3) |
JTAG_TMSC | 24 | I/O | Digital | JTAG TMSC, high-drive capability |
JTAG_TCKC | 25 | I | Digital | JTAG TCKC |
RESET_N | 35 | I | Digital | Reset, active low. No internal pullup resistor |
RF_P_2_4GHZ | 1 | — | RF | Positive 2.4-GHz RF input signal to LNA during RX Positive 2.4-GHz RF output signal from PA during TX |
RF_N_2_4GHZ | 2 | — | RF | Negative 2.4-GHz RF input signal to LNA during RX Negative 2.4-GHz RF output signal from PA during TX |
RF_P_SUB_1GHZ | 3 | — | RF | Positive Sub-1 GHz RF input signal to LNA during RX Positive Sub-1 GHz RF output signal from PA during TX |
RF_N_SUB_1GHZ | 4 | — | RF | Negative Sub-1 GHz RF input signal to LNA during RX Negative Sub-1 GHz RF output signal from PA during TX |
RX_TX | 7 | — | RF | Optional bias pin for the RF LNA |
TX_20DBM_P | 5 | — | RF | Positive Sub-1 GHz or 2.4-GHz high-power TX signal |
TX_20DBM_N | 6 | — | RF | Negative Sub-1 GHz or 2.4-GHz high-power TX signal |
VDDR | 45 | — | Power | Internal supply, must be powered from the internal DC/DC converter or the internal LDO(2)(4)(6) |
VDDR_RF | 48 | — | Power | Internal supply, must be powered from the internal DC/DC converter or the internal LDO(2)(5)(6) |
VDDS | 44 | — | Power | 1.8-V to 3.8-V main chip supply(1) |
VDDS2 | 13 | — | Power | 1.8-V to 3.8-V DIO supply(1) |
VDDS3 | 22 | — | Power | 1.8-V to 3.8-V DIO supply(1) |
VDDS_DCDC | 34 | — | Power | 1.8-V to 3.8-V DC/DC converter supply |
X48M_N | 46 | — | Analog | 48-MHz crystal oscillator pin 1 |
X48M_P | 47 | — | Analog | 48-MHz crystal oscillator pin 2 |
X32K_Q1 | 8 | — | Analog | 32-kHz crystal oscillator pin 1 |
X32K_Q2 | 9 | — | Analog | 32-kHz crystal oscillator pin 2 |