JAJSFW0F July   2018  – February 2021 CC1352P

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Functional Block Diagram
  5. 5 改訂履歴
  6. 6 Device Comparison
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram – RGZ Package (Top View)
    2. 7.2 Signal Descriptions – RGZ Package
    3. 7.3 Connections for Unused Pins and Modules
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Power Supply and Modules
    5. 8.5  Power Consumption - Power Modes
    6. 8.6  Power Consumption - Radio Modes
    7. 8.7  Nonvolatile (Flash) Memory Characteristics
    8. 8.8  Thermal Resistance Characteristics
    9. 8.9  RF Frequency Bands
    10. 8.10 861 MHz to 1054 MHz - Receive (RX)
    11. 8.11 861 MHz to 1054 MHz - Transmit (TX) 
    12. 8.12 861 MHz to 1054 MHz - PLL Phase Noise Wideband Mode
    13. 8.13 861 MHz to 1054 MHz - PLL Phase Noise Narrowband Mode
    14. 8.14 359 MHz to 527 MHz - Receive (RX)
    15. 8.15 359 MHz to 527 MHz - Transmit (TX) 
    16. 8.16 359 MHz to 527 MHz - PLL Phase Noise
    17. 8.17 143 MHz to 176 MHz - Receive (RX)
    18. 8.18 143 MHz to 176 MHz  - Transmit (TX) 
    19. 8.19 143 MHz to 176 MHz - PLL Phase Noise
    20. 8.20 Bluetooth Low Energy - Receive (RX)
    21. 8.21 Bluetooth Low Energy - Transmit (TX)
    22. 8.22 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - RX
    23. 8.23 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - TX
    24. 8.24 Timing and Switching Characteristics
      1. 8.24.1 Reset Timing
      2. 8.24.2 Wakeup Timing
      3. 8.24.3 Clock Specifications
        1. 8.24.3.1 48 MHz Clock Input (TCXO)
        2. 8.24.3.2 48 MHz Crystal Oscillator (XOSC_HF)
        3. 8.24.3.3 48 MHz RC Oscillator (RCOSC_HF)
        4. 8.24.3.4 2 MHz RC Oscillator (RCOSC_MF)
        5. 8.24.3.5 32.768 kHz Crystal Oscillator (XOSC_LF)
        6. 8.24.3.6 32 kHz RC Oscillator (RCOSC_LF)
      4. 8.24.4 Synchronous Serial Interface (SSI) Characteristics
        1. 8.24.4.1 Synchronous Serial Interface (SSI) Characteristics
        2.       47
      5. 8.24.5 UART
        1. 8.24.5.1 UART Characteristics
    25. 8.25 Peripheral Characteristics
      1. 8.25.1 ADC
        1. 8.25.1.1 Analog-to-Digital Converter (ADC) Characteristics
      2. 8.25.2 DAC
        1. 8.25.2.1 Digital-to-Analog Converter (DAC) Characteristics
      3. 8.25.3 Temperature and Battery Monitor
        1. 8.25.3.1 Temperature Sensor
        2. 8.25.3.2 Battery Monitor
      4. 8.25.4 Comparators
        1. 8.25.4.1 Low-Power Clocked Comparator
        2. 8.25.4.2 Continuous Time Comparator
      5. 8.25.5 Current Source
        1. 8.25.5.1 Programmable Current Source
      6. 8.25.6 GPIO
        1. 8.25.6.1 GPIO DC Characteristics
    26. 8.26 Typical Characteristics
      1. 8.26.1 MCU Current
      2. 8.26.2 RX Current
      3. 8.26.3 TX Current
      4. 8.26.4 RX Performance
      5. 8.26.5 TX Performance
      6. 8.26.6 ADC Performance
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  System CPU
    3. 9.3  Radio (RF Core)
      1. 9.3.1 Proprietary Radio Formats
      2. 9.3.2 Bluetooth 5.2 Low Energy
      3. 9.3.3 802.15.4 (Thread, Zigbee, 6LoWPAN)
    4. 9.4  Memory
    5. 9.5  Sensor Controller
    6. 9.6  Cryptography
    7. 9.7  Timers
    8. 9.8  Serial Peripherals and I/O
    9. 9.9  Battery and Temperature Monitor
    10. 9.10 µDMA
    11. 9.11 Debug
    12. 9.12 Power Management
    13. 9.13 Clock Systems
    14. 9.14 Network Processor
  10. 10Application, Implementation, and Layout
    1. 10.1 Reference Designs
  11. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
      1. 11.2.1 SimpleLink™ Microcontroller Platform
    3. 11.3 Documentation Support
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

9.11 Debug

The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface. The device boots by default into cJTAG mode and must be reconfigured to use 4-pin JTAG.