JAJSFW0F July 2018 – February 2021 CC1352P
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | TYP | UNIT | |
---|---|---|---|---|
Core Current Consumption | ||||
Icore | Reset and Shutdown | Reset. RESET_N pin asserted or VDDS below power-on-reset threshold | 150 | nA |
Shutdown. No clocks running, no retention | 150 | |||
Standby without cache retention |
RTC running, CPU, 80KB RAM and (partial) register retention. RCOSC_LF |
0.85 | µA | |
RTC running, CPU, 80KB RAM and (partial) register retention XOSC_LF |
0.99 | µA | ||
Standby with cache retention |
RTC running, CPU, 80KB RAM and (partial) register retention. RCOSC_LF |
2.78 | µA | |
RTC running, CPU, 80KB RAM and (partial) register retention. XOSC_LF |
2.92 | µA | ||
Idle | Supply Systems and RAM powered RCOSC_HF |
590 | µA | |
Active | MCU running CoreMark at 48 MHz RCOSC_HF |
2.89 | mA | |
Peripheral Current Consumption 1, 2 | ||||
Iperi | Peripheral power domain | Delta current with domain enabled | 82.3 | µA |
Serial power domain | Delta current with domain enabled | 5.5 | ||
RF Core | Delta current with power domain enabled, clock enabled, RF core idle |
178.9 | ||
µDMA | Delta current with clock enabled, module is idle | 53.6 | ||
Timers | Delta current with clock enabled, module is idle(5) | 67.8 | ||
I2C | Delta current with clock enabled, module is idle | 8.2 | ||
I2S | Delta current with clock enabled, module is idle | 21.7 | ||
SSI | Delta current with clock enabled, module is idle(4) | 69.4 | ||
UART | Delta current with clock enabled, module is idle(3) | 140.8 | ||
CRYPTO (AES) | Delta current with clock enabled, module is idle | 21.1 | ||
PKA | Delta current with clock enabled, module is idle | 71.1 | ||
TRNG | Delta current with clock enabled, module is idle | 29.7 | ||
Sensor Controller Engine Consumption | ||||
ISCE | Active mode | 24 MHz, infinite loop, VDDS = 3.0 V | 808.5 | µA |
Low-power mode | 2 MHz, infinite loop, VDDS = 3.0 V | 30.1 |