JAJSG17D June 2014 – August 2018 MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR59891 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
feUSCI | eUSCI input clock frequency | Internal: SMCLK or ACLK,
External: UCLK, Duty cycle = 50% ±10% |
16 | MHz | |||
fSCL | SCL clock frequency | 2.2 V, 3.0 V | 0 | 400 | kHz | ||
tHD,STA | Hold time (repeated) START | fSCL = 100 kHz | 2.2 V, 3.0 V | 4.0 | µs | ||
fSCL > 100 kHz | 0.6 | ||||||
tSU,STA | Setup time for a repeated START | fSCL = 100 kHz | 2.2 V, 3.0 V | 4.7 | µs | ||
fSCL > 100 kHz | 0.6 | ||||||
tHD,DAT | Data hold time | 2.2 V, 3.0 V | 0 | ns | |||
tSU,DAT | Data setup time | 2.2 V, 3.0 V | 100 | ns | |||
tSU,STO | Setup time for STOP | fSCL = 100 kHz | 2.2 V, 3.0 V | 4.0 | µs | ||
fSCL > 100 kHz | 0.6 | ||||||
tBUF | Bus free time between STOP and START conditions | fSCL = 100 kHz | 4.7 | µs | |||
fSCL > 100 kHz | 1.3 | ||||||
tSP | Pulse duration of spikes suppressed by input filter | UCGLITx = 0 | 2.2 V, 3.0 V | 50 | 250 | ns | |
UCGLITx = 1 | 25 | 125 | |||||
UCGLITx = 2 | 12.5 | 62.5 | |||||
UCGLITx = 3 | 6.3 | 31.5 | |||||
tTIMEOUT | Clock low time-out | UCCLTOx = 1 | 2.2 V, 3.0 V | 27 | ms | ||
UCCLTOx = 2 | 30 | ||||||
UCCLTOx = 3 | 33 |