JAJSG21C August   2019  – October 2024 TCAN1044-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Characteristics
    6. 5.6  Supply Characteristics
    7. 5.7  Dissipation Ratings
    8. 5.8  Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pin Description
        1. 7.3.1.1 TXD
        2. 7.3.1.2 GND
        3. 7.3.1.3 VCC
        4. 7.3.1.4 RXD
        5. 7.3.1.5 VIO
        6. 7.3.1.6 CANH and CANL
        7. 7.3.1.7 STB (Standby)
      2. 7.3.2 CAN Bus States
      3. 7.3.3 TXD Dominant Timeout (DTO)
      4. 7.3.4 CAN Bus Short Circuit Current Limiting
      5. 7.3.5 Thermal Shutdown (TSD)
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 Unpowered Device
      8. 7.3.8 Floating pins
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 Normal Mode
      3. 7.4.3 Standby Mode
        1. 7.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
      4. 7.4.4 Driver and Receiver Function
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 CAN Termination
      2. 8.2.2 Detailed Design Procedures
        1. 8.2.2.1 Bus Loading, Length and Number of Nodes
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 商標
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.2 CAN Bus States

The CAN bus has two logical states during operation: recessive and dominant. See Figure 7-2 and Figure 7-3.

A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD and RXD pins. A recessive bus state occurs when the bus is biased to VCC/2 via the high-resistance internal input resistors RIN) of the receiver and corresponds to a logic high on the TXD and RXD pins.

A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a dominant bit at the same time during arbitration, and in this case the differential voltage of the bus is greater than the differential voltage of a single driver.

The TCAN1044-Q1 transceiver implements a low-power standby (STB) mode which enables a third bus state where the bus pins are weakly biased to ground via the high resistance internal resistors of the receiver. See Figure 7-2 and Figure 7-3.

TCAN1044-Q1 Bus StatesFigure 7-2 Bus States
TCAN1044-Q1 Simplified Recessive Common Mode Bias Unit and Receiver
A. Normal Mode
B. Standby Mode
Figure 7-3 Simplified Recessive Common Mode Bias Unit and Receiver