JAJSG84B January 2016 – June 2018 LP8758-E0
PRODUCTION DATA.
The LP8758-E0 is controlled by a set of registers through the serial interface port. The device registers, their addresses and their abbreviations are listed in Table 6. A more detailed description is given in sections OTP_REV to I_LOAD_1.
The asterisk (*) marking indicates register bits which are updated from OTP memory during READ OTP state.
Addr | Register | Read / Write | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|---|---|
0x01 | OTP_REV | R | OTP_ID[7:0] | |||||||
0x02 | BUCK0_
CTRL1 |
R/W | EN_BUCK0 | EN_PIN_
CTRL0 |
EN_PIN_
SELECT0 |
EN_ROOF
_FLOOR0 |
EN_RDIS0 | Reserved | BUCK0_
FPWM |
Reserved |
0x03 | BUCK0_
CTRL2 |
R/W | Reserved | ILIM0[2:0] | SLEW_RATE0[2:0] | |||||
0x04 | BUCK1_
CTRL1 |
R/W | EN_BUCK1 | EN_PIN_
CTRL1 |
EN_PIN_
SELECT1 |
EN_ROOF
_FLOOR1 |
EN_RDIS1 | Reserved | BUCK1_
FPWM |
Reserved |
0x05 | BUCK1_
CTRL2 |
R/W | Reserved | ILIM1[2:0] | SLEW_RATE1[2:0] | |||||
0x06 | BUCK2_
CTRL1 |
R/W | EN_BUCK2 | EN_PIN_
CTRL2 |
EN_PIN_
SELECT2 |
EN_ROOF
_FLOOR2 |
EN_RDIS2 | Reserved | BUCK2_
FPWM |
Reserved |
0x07 | BUCK2_
CTRL2 |
R/W | Reserved | ILIM2[2:0] | SLEW_RATE2[2:0] | |||||
0x08 | BUCK3_
CTRL1 |
R/W | EN_BUCK3 | EN_PIN_
CTRL3 |
EN_PIN_
SELECT3 |
EN_ROOF
_FLOOR3 |
EN_RDIS3 | Reserved | BUCK3_
FPWM |
Reserved |
0x09 | BUCK3_
CTRL2 |
R/W | Reserved | ILIM3[2:0] | SLEW_RATE3[2:0] | |||||
0x0A | BUCK0_
VOUT |
R/W | BUCK0_VSET[7:0] | |||||||
0x0B | BUCK0_
FLOOR_ VOUT |
R/W | BUCK0_FLOOR_VSET[7:0] | |||||||
0x0C | BUCK1_
VOUT |
R/W | BUCK1_VSET[7:0] | |||||||
0x0D | BUCK1_
FLOOR_ VOUT |
R/W | BUCK1_FLOOR_VSET[7:0] | |||||||
0x0E | BUCK2_
VOUT |
R/W | BUCK2_VSET[7:0] | |||||||
0x0F | BUCK2_
FLOOR_ VOUT |
R/W | BUCK2_FLOOR_VSET[7:0] | |||||||
0x10 | BUCK3_
VOUT |
R/W | BUCK3_VSET[7:0] | |||||||
0x11 | BUCK3_
FLOOR_ VOUT |
R/W | BUCK3_FLOOR_VSET[7:0] | |||||||
0x12 | BUCK0_
DELAY |
R/W | BUCK0_SHUTDOWN_DELAY[3:0] | BUCK0_STARTUP_DELAY[3:0] | ||||||
0x13 | BUCK1_
DELAY |
R/W | BUCK1_SHUTDOWN_DELAY[3:0] | BUCK1_STARTUP_DELAY[3:0] | ||||||
0x14 | BUCK2_
DELAY |
R/W | BUCK2_SHUTDOWN_DELAY[3:0] | BUCK2_STARTUP_DELAY[3:0] | ||||||
0x15 | BUCK3_
DELAY |
R/W | BUCK3_SHUTDOWN_DELAY[3:0] | BUCK3_STARTUP_DELAY[3:0] | ||||||
0x16 | RESET | R/W | Reserved | SW_
RESET |
||||||
0x17 | CONFIG | R/W | Reserved | TDIE
_WARN _LEVEL |
EN2_PD | EN1_PD | EN_
SPREAD _SPEC |
|||
0x18 | INT_TOP | R/W | INT_
BUCK3 |
INT_
BUCK2 |
INT_
BUCK1 |
INT_
BUCK0 |
TDIE_SD | TDIE_
WARN |
RESET_
REG |
I_LOAD_
READY |
0x19 | INT_BUCK_0_1 | R/W | Reserved | BUCK1_
PG_INT |
BUCK1_
SC_INT |
BUCK1_
ILIM_INT |
Reserved | BUCK0_
PG_INT |
BUCK0_
SC_INT |
BUCK0_
ILIM_INT |
0x1A | INT_BUCK_2_3 | R/W | Reserved | BUCK3_
PG_INT |
BUCK3_
SC_INT |
BUCK3_
ILIM_INT |
Reserved | BUCK2_
PG_INT |
BUCK2_
SC_INT |
BUCK2_
ILIM_INT |
0x1B | TOP_
STAT |
R | Reserved | TDIE_SD
_STAT |
TDIE_
WARN_ STAT |
Reserved | ||||
0x1C | BUCK_0_1_STAT | R | BUCK1_
STAT |
BUCK1_
PG_STAT |
Reserved | BUCK1_
ILIM_ STAT |
BUCK0_
STAT |
BUCK0_
PG_STAT |
Reserved | BUCK0_
ILIM_ STAT |
0x1D | BUCK_2_3_STAT | R | BUCK3_
STAT |
BUCK3_
PG_STAT |
Reserved | BUCK3_
ILIM_STAT |
BUCK2_
STAT |
BUCK2_
PG_STAT |
Reserved | BUCK2_
ILIM_STAT |
0x1E | TOP_
MASK |
R/W | Reserved | TDIE_WARN_MASK | RESET_
REG_MASK |
I_LOAD_
READY_ MASK |
||||
0x1F | BUCK_0_1_MASK | R/W | Reserved | BUCK1_
PG_MASK |
Reserved | BUCK1_
ILIM_ MASK |
Reserved | BUCK0_
PG_MASK |
Reserved | BUCK0_
ILIM_ MASK |
0x20 | BUCK_2_3_MASK | R/W | Reserved | BUCK3_
PG_MASK |
Reserved | BUCK3_
ILIM_ MASK |
Reserved | BUCK2_
PG_MASK |
Reserved | BUCK2_
ILIM_ MASK |
0x21 | SEL_I_
LOAD |
R/W | Reserved | LOAD_CURRENT_
BUCK_SELECT[1:0] |
||||||
0x22 | I_LOAD_2 | R/W | Reserved | BUCK_LOAD_CURRENT[9:8] | ||||||
0x23 | I_LOAD_1 | R/W | BUCK_LOAD_CURRENT[7:0] |