JAJSG99 September 2018 ADS1235
PRODUCTION DATA.
The digital filter averages data from the modulator in order to produce the conversion result. The stages of the digital filter must have settled data in order to provide fully-settled output data. The order and the decimation ratio of the digital filter determine the amount of data averaged, and in turn, affect the latency of the conversion data. The FIR and sinc1 filter modes are zero latency because the ADC provides the conversion result in one conversion cycle. Latency time is an important consideration for the data throughput rate in multiplexed applications.
Table 6 lists the conversion latency values of the ADC. Conversion latency is defined as the time from the start of the first conversion, by taking the START pin high or sending the START command, to the time when fully settled conversion data are ready. If the input signal is settled, then the ADC provides fully settled data. The conversion latency values listed in the table are with the start-conversion delay parameter = 50 µs, and include the overhead time needed to process the data. After the first conversion completes (in continuous conversion mode), the period of the following conversions are equal to 1/fDATA. The first conversion latency in chop and ac-excitation modes are twice the values listed in the table. Also when operating in these modes, the period of following conversions are equal to the values listed in the table.
DATA RATE
(SPS) |
CONVERSION LATENCY - t(STDR)(1) (ms) | ||||
---|---|---|---|---|---|
FIR | SINC1 | SINC2 | SINC3 | SINC4 | |
2.5 | 402.2 | 400.4 | 800.4 | 1,200 | 1,600 |
5 | 202.2 | 200.4 | 400.4 | 600.4 | 800.4 |
10 | 102.2 | 100.4 | 200.4 | 300.4 | 400.4 |
16.6 | — | 60.43 | 120.4 | 180.4 | 240.4 |
20 | 52.23 | 50.43 | 100.4 | 150.4 | 200.4 |
50 | — | 20.43 | 40.43 | 60.43 | 80.43 |
60 | — | 17.09 | 33.76 | 50.43 | 67.09 |
100 | — | 10.43 | 20.43 | 30.43 | 40.43 |
400 | — | 2.925 | 5.425 | 7.925 | 10.43 |
1200 | — | 1.258 | 2.091 | 2.925 | 3.758 |
2400 | — | 0.841 | 1.258 | 1.675 | 2.091 |
4800 | — | 0.633 | 0.841 | 1.050 | 1.258 |
7200 | — | 0.564 | 0.702 | 0.841 | 0.980 |
If the input signal changes while free-running conversions, the conversion data are a mix of old and new data, as shown in Figure 58. After an input change, the number of conversion periods required for fully settled data are determined by dividing the conversion latency by the period of the data rate, plus add one conversion period to the result. In chop and ac-bridge excitation modes, use twice the latency values listed in the table.