JAJSGI4 データシート

JAJSGI4B November 2018 – March 2021 ADC12DJ3200QML-SP

PRODUCTION DATA

Table 7-138 SYSREF Calibration Registers

ADDRESS	RESET	ACRONYM	REGISTER NAME	SECTION
0x2B0	0x00	SRC_EN	SYSREF Calibration Enable Register	Section 7.6.2.1
0x2B1	0x05	SRC_CFG	SYSREF Calibration Configuration Register	Section 7.6.2.2
0x2B2-0x2B4	Undefined	SRC_STATUS	SYSREF Calibration Status	Section 7.6.2.3
0x2B5-0x2B7	0x00	TAD	DEVCLK Aperture Delay Adjustment Register	Section 7.6.2.4
0x2B8	0x00	TAD_RAMP	DEVCLK Timing Adjust Ramp Control Register	Section 7.6.2.5
0x2B9-0x2BF	Undefined	RESERVED	RESERVED	—

7.6.2.1 SYSREF Calibration Enable Register (address = 0x2B0) [reset = 0x00]

Figure 7-110 SYSREF Calibration Enable Register (SRC_EN)

Table 7-139 SRC_EN Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	0000 000	RESERVED
0	SRC_EN	R/W	0	0: SYSREF calibration disabled; use the TAD register to manually control the TAD[16:0] output and adjust the DEVCLK delay (default) 1: SYSREF calibration enabled; the DEVCLK delay is automatically calibrated; the TAD register is ignored A 0-to-1 transition on SRC_EN starts the SYSREF calibration sequence. Program SRC_CFG before setting SRC_EN. Ensure that ADC calibration is not currently running before setting SRC_EN.

Figure 7-111 SYSREF Calibration Configuration Register (SRC_CFG)

Table 7-140 SRC_CFG Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	0000 00	RESERVED
3-2	SRC_AVG	R/W	01	Specifies the amount of averaging used for SYSREF calibration. Larger values increase calibration time and reduce the variance of the calibrated value. 0: 4 averages 1: 16 averages 2: 64 averages 3: 256 averages
1-0	SRC_HDUR	R/W	01	Specifies the duration of each high-speed accumulation for SYSREF Calibration. If the SYSREF period exceeds the supported value, the calibration fails. Larger values increase calibration time and support longer SYSREF periods. For a given SYSREF period, larger values also reduce the variance of the calibrated value. 0: 4 cycles per accumulation, max SYSREF period of 85 DEVCLK cycles 1: 16 cycles per accumulation, max SYSREF period of 1100 DEVCLK cycles 2: 64 cycles per accumulation, max SYSREF period of 5200 DEVCLK cycles 3: 256 cycles per accumulation, max SYSREF period of 21580 DEVCLK cycles Max duration of SYSREF calibration is bounded by: T_SYSREFCAL (in DEVCLK cycles) = 256 × 19 × 4^{(SRC_AVG + SRC_HDUR + 2)}

Figure 7-112 SYSREF Calibration Status Register (SRC_STATUS)

Table 7-141 SRC_STATUS Field Descriptions

Bit	Field	Type	Reset	Description
23-18	RESERVED	R	Undefined	RESERVED
17	SRC_DONE	R	Undefined	This bit returns a 1 when SRC_EN = 1 and SYSREF calibration is complete.
16-0	SRC_TAD	R	Undefined	This field returns the value for TAD[16:0] computed by the SYSREF calibration. This field is only valid if SRC_DONE = 1.

Figure 7-113 DEVCLK Aperture Delay Adjustment Register (TAD)

Table 7-142 TAD Field Descriptions

Bit	Field	Type	Reset	Description
23-17	RESERVED	R/W	0000 000	RESERVED
16	TAD_INV	R/W	0	Invert DEVCLK by setting this bit equal to 1.
15-8	TAD_COARSE	R/W	0000 0000	This register controls the DEVCLK aperture delay adjustment when SRC_EN = 0. Use this register to manually control the DEVCLK aperture delay when SYSREF calibration is disabled. If ADC calibration or JESD204B is running, TI recommends gradually increasing or decreasing this value (1 code at a time) to avoid clock glitches. See the GUID-44D20AC7-3E18-402E-B9FD-7CECECE51C0D.html#GUID-44D20AC7-3E18-402E-B9FD-7CECECE51C0D table for TAD_COARSE resolution.
7-0	TAD_FINE	R/W	0000 0000	See the GUID-44D20AC7-3E18-402E-B9FD-7CECECE51C0D.html#GUID-44D20AC7-3E18-402E-B9FD-7CECECE51C0D table for TAD_FINE resolution.

Figure 7-114 DEVCLK Timing Adjust Ramp Control Register (TAD_RAMP)

Table 7-143 TAD_RAMP Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R/W	0000 00	RESERVED
1	TAD_RAMP_RATE	R/W	0	Specifies the ramp rate for the TAD[15:8] output when the TAD[15:8] register is written when TAD_RAMP_EN = 1. 0: TAD[15:8] ramps up or down one code per 256 DEVCLK cycles. 1: TAD[15:8] ramps up or down 4 codes per 256 DEVCLK cycles.
0	TAD_RAMP_EN	R/W	0	TAD ramp enable. Set this bit if coarse TAD adjustments are desired to ramp up or down instead of changing abruptly. 0: After writing the TAD[15:8] register the aperture delay is updated within 1024 DEVCLK cycles 1: After writing the TAD[15:8] register the aperture delay ramps up or down until the aperture delay matches the TAD[15:8] register