JAJSGJ7B October   2017  – July 2019 ISO7041

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      簡略化されたアプリケーション回路図
      2.      3.3V時のデータ・レートと消費電力との関係
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics 5V Supply
    10. 7.10 Supply Current Characteristics 5V Supply
    11. 7.11 Electrical Characteristics 3.3V Supply
    12. 7.12 Supply Current Characteristics 3.3V Supply
    13. 7.13 Electrical Characteristics 2.5V Supply
    14. 7.14 Supply Current Characteristics 2.5V Supply
    15. 7.15 Switching Characteristics
    16. 7.16 Insulation Characteristics Curves
    17. 7.17 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Refresh Enable
      2. 9.3.2 Electromagnetic Compatibility (EMC) Considerations
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematics
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Insulation Lifetime
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

9.3.1 Refresh Enable

The ISO7041 uses an edge based encoding scheme to transfer an input signal change across the isolation barrier versus sending across the DC state. consistently validates that the DC output state of each isolator channel matches the DC input state. An internal watchdog timer monitors for activity on the individual inputs and transmits the logic state when there is no input signal transition for more than 100 µs. This ensures that the input and output state of the isolator always match. Tie both EN1 and EN2 to their respective grounds to enable refresh.

Disable refresh by tying both EN1 and EN2 to their respective VCC power supplies. Disabling refresh will further decrease the power consumption of the device but the DC state is not guaranteed at startup. System level solutions can be implemented to ensure the isolator channel output matches the input at startup. For example, at start up, an immediate full transition of the input signals from high to low and low to high on the individual isolator lines would allow the states of the outputs to properly track the inputs.