JAJSGL5C
December 2018 – August 2019
TPS3840
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
代表的なアプリケーション回路
TPS3840 の標準的な消費電流
4
改訂履歴
5
概要 (続き)
6
Device Comparison Table
7
Pin Configuration and Functions
Pin Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing Requirements
8.7
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Input Voltage (VDD)
9.3.1.1
VDD Hysteresis
9.3.1.2
VDD Transient Immunity
9.3.2
User-Programmable Reset Time Delay
9.3.3
Manual Reset (MR) Input
9.3.4
Output Logic
9.3.4.1
RESET Output, Active-Low
9.3.4.2
RESET Output, Active-High
9.4
Device Functional Modes
9.4.1
Normal Operation (VDD > VDD(min))
9.4.2
VDD Between VPOR and VDD(min)
9.4.3
Below Power-On-Reset (VDD < VPOR)
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design 1: Dual Rail Monitoring with Power-Up Sequencing
10.2.1.1
Design Requirements
10.2.1.2
Detailed Design Procedure
10.2.1.3
Application Curves
10.2.2
Design 2: Battery Voltage and Temperature Monitor
10.2.2.1
Design Requirements
10.2.2.2
Detailed Design Procedure
10.2.3
Design 3: Fast Start Undervoltage Supervisor with Level-shifted Input
10.2.3.1
Design Requirements
10.2.3.2
Detailed Design Procedure
10.2.4
Design 4: Voltage Monitor with Back-up Battery Switchover
10.2.4.1
Design Requirements
10.2.4.2
Detailed Design Procedure
10.2.5
Application Curve: TPS3840EVM
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
デバイスおよびドキュメントのサポート
13.1
デバイスの項目表記
13.2
コミュニティ・リソース
13.3
商標
13.4
静電気放電に関する注意事項
13.5
Glossary
14
メカニカル、パッケージ、および注文情報
9.2
Functional Block Diagram