JAJSGL5C December   2018  – August 2019 TPS3840

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
      2.      TPS3840 の標準的な消費電流
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input Voltage (VDD)
        1. 9.3.1.1 VDD Hysteresis
        2. 9.3.1.2 VDD Transient Immunity
      2. 9.3.2 User-Programmable Reset Time Delay
      3. 9.3.3 Manual Reset (MR) Input
      4. 9.3.4 Output Logic
        1. 9.3.4.1 RESET Output, Active-Low
        2. 9.3.4.2 RESET Output, Active-High
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Operation (VDD > VDD(min))
      2. 9.4.2 VDD Between VPOR and VDD(min)
      3. 9.4.3 Below Power-On-Reset (VDD < VPOR)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Design 2: Battery Voltage and Temperature Monitor
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
      3. 10.2.3 Design 3: Fast Start Undervoltage Supervisor with Level-shifted Input
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
      4. 10.2.4 Design 4: Voltage Monitor with Back-up Battery Switchover
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedure
      5. 10.2.5 Application Curve: TPS3840EVM
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイスの項目表記
    2. 13.2 コミュニティ・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報

10.2.3 Design 3: Fast Start Undervoltage Supervisor with Level-shifted Input

A typical application for the TPS3840 is a fast startup undervoltage supervisor that operates with an input power supply higher than the recommended maximum of 10 V through the use of a resistor divider at the input as shown in Figure 51. The TPS3840 can be used to monitor any rail above 1.6 V and only requires maximum 350 µs upon startup before the device can begin monitoring a voltage. In this design application, a TPS3840 monitors a 12-V rail and triggers a reset fault condition if the voltage rail voltage drops below 10 V using a TPS3840 device with VIT- of 4.9 V. This design also accounts for a wide input range in the case the 12-V rail rises higher, the resistor divider is set so that the voltage at the VDD pin never exceeds 10 V. The resistor values must not be so large that the external resistor divider affects the accuracy or operation of the device. TPS3840 is available in both active-low and active-high topologies providing the flexibility to monitor undervoltage or overvoltage with either output logic. This design uses the active-low, open-drain TPS3840DL49 variant so that when the undervoltage condition occurs, that is when the voltage at VDD pin falls below the voltage threshold set by the external resistor divider, the output transitions to logic-low and can be used to flag an undervoltage condition or used to connect to the ENABLE of the next device to shut it off as a logic low on an ENABLE pin typically disables the device. In this design, the output of the TPS3840 simply connects to a MCU to flag an undervoltage condition.

TPS3840 Typical_Application_3.gifFigure 51. Fast Start Undervoltage Supervisor with Level-shifted Input