JAJSGO0C February 2018 – September 2019 BQ25882
PRODUCTION DATA.
REG00 is shown in Figure 37 and described in Table 9.
Return to Summary Table.
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
Field | VREG[7:0] |
Bit | Field | Type | Reset by REG_RST | Reset by WATCHDOG | Description | |
---|---|---|---|---|---|---|
7 | VREG[7] | R/W | Yes | Yes | 1280 mV |
Charge voltage limit
|
6 | VREG[6] | R/W | Yes | Yes | 640 mV | |
5 | VREG[5] | R/W | Yes | Yes | 320 mV | |
4 | VREG[4] | R/W | Yes | Yes | 160 mV | |
3 | VREG[3] | R/W | Yes | Yes | 80 mV | |
2 | VREG[2] | R/W | Yes | Yes | 40 mV | |
1 | VREG[1] | R/W | Yes | Yes | 20 mV | |
0 | VREG[0] | R/W | Yes | Yes | 10 mV |