JAJSGO0C February 2018 – September 2019 BQ25882
PRODUCTION DATA.
REG05 is shown in Figure 42 and described in Table 14.
Return to Summary Table.
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 |
Field | EN_TERM | RESERVED | WATCHDOG[1:0] | EN_TIMER | CHG_TIMER[1:0] | TMR2X_EN |
Bit | Field | Type | Reset by REG_RST | Reset by WATCHDOG | Description | |
---|---|---|---|---|---|---|
7 | EN_TERM | R/W | Yes | Yes | Termination Control:
0 – Disable termination 1 – Enable termination (default) |
|
6 | RESERVED | R/W | Yes | Yes | Reserved bit always reads 0 | |
5 | WATCHDOG[1] | R/W | Yes | Yes | I2C Watchdog Timer Settings:
00 – Disable WD Timer 01 – 40s (default) 10 – 80s 11 – 160s |
|
4 | WATCHDOG[0] | R/W | Yes | Yes | ||
3 | EN_TIMER | R/W | Yes | Yes | Charging Safety Timer Enable
0 – Disable 1 – Enable (Default) |
|
2 | CHG_TIMER[1] | R/W | Yes | Yes | Fast Charge Timer Setting
00 – 5 hrs 01 – 8 hrs 10 – 12 hrs (Default) 11 – 20 hrs |
|
1 | CHG_TIMER[0] | R/W | Yes | Yes | ||
0 | TMR2X_EN | R/W | Yes | Yes | Safety Timer during DPM or TREG
0 – Safety timer always count normally 1 – Safety timer slowed by 2X during input DPM or TREG (Default) |
System Note: When the WATCHDOG bits are changed (writing the same value does not change WATCHDOG bit), the internal counter is reset. The same applies for the CHG_TIMER bits. Only changing the value in the register will reset the CHG_TIMER