8.6.52 CDLAR1_Register Register (Offset = 0x185) [reset = 0x0]
CDLAR1_Register is shown in Table 64.
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Table 64. CDLAR1_Register Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
15-7 |
RESERVED |
R |
0x0 |
Reserved
|
6-0 |
TD_Peak_Amplitude_1 |
|
0x0 |
Amplitude of the First peak discovered by the TDR mechanism on Transmit Channel (TD). The value of these bits is translated into type of cable fault and/or interference.
|