JAJSGP5 データシート

JAJSGP5A December 2018 – August 2019 DP83825I

PRODUCTION DATA.

7.6 Timing Requirements

PARAMETER		MIN	NOM	MAX	UNIT
POWER-UP TIMING
T1	Voltage Ramp Duration ( 0 to 100% VDDIO)⁽¹⁾	0.5		40	ms
T2	Supply Sequencing AVDD followed by VDDIO			200	ms
T3	Voltage Ramp Duration ( 0 to 100% of AVDD)	0.5		40	ms
T4	POR release time / Powerup to SMI ready: Post power-up stabilization time prior to MDC preamble for register access			50	ms
T5	Powerup to FLP		1500		ms
	Pedestal Voltage on AVDD, VDDIO before Power Ramp			0.3	V
RESET TIMING
T1	RESET PULSE Width: Miminum Reset pulse width to be able to reset (w/o debouncing caps)	25			us
T2	Reset to SMI ready: Post reset stabilization time prior to MDC preamble for register access			2	ms
T3	Reset to FLP		1500		ms
	Reset to 100M signaling (strapped mode)		0.5		ms
	Reset to RMII Master clock		0.2		ms
100M EEE timings
	Sleep time (Ts)		210		us
	Quiet time (Tq)		20		ms
	Refresh time (Tr)		200		us
	Wake time (Tw_sys_tx)		36		us
RMII Master TIMING (100M)
	RMII Master Clock Period		20		ns
	RMII Master Clock Duty Cycle	35		65	%
T2	TX_D[1:0], TX_ER, TX_EN Setup to RMII Master Clock	4			ns
T3	TX_D[1:0], TX_ER, TX_EN Hold from RMII Master Clock	2			ns
T4	RX_D[1:0], RX_ER, CRS_DV Delay from RMII Master Clock rising edge	4	10	14	ns
RMII Slave TIMING (100M)
T1	Input Reference Clock Period		20		ns
	Reference Clock Duty Cycle	35		65	%
T2	TX_D[1:0], TX_ER, TX_EN Setup to XI Clock rising⁽²⁾	4			ns
T3	TX_D[1:0], TX_ER, TX_EN Hold from XI Clock rising	2			ns
T4	RX_D[1:0], RX_ER, CRS_DV Delay from XI Clock rising	4		14	ns
SMI TIMING
T1	MDC to MDIO (Output) Delay Time	0		10	ns
T2	MDIO (Input) to MDC Setup Time	10			ns
T3	MDIO (Input) to MDC Hold Time	10			ns
T4	MDC Frequency		2.5	20	MHz
OUTPUT CLOCK TIMING (50M RMII Master Clock)
	Frequency (PPM)	-50		50	ppm
	Duty Cycle	35		65	%
	Rise time			4000	ps
	Fall Time			4000	ps
	Jitter (Long Term)			450	ps
	RefCLK to clock out delay with multiple resets			40	ns
INPUT CLOCK tolerance
25MHz	Frequency Tolerance	-50		50	ppm
	Rise / Fall Time			5	ns
	Jitter Tolerance (Accumulated over 100,000 cycles)			1.75	ns
	Duty Cycle	40		60	%
	input phase noise at 1KHz			-98	dBc/Hz
	input phase noise at 10KHz			-113	dBc/Hz
	input phase noise at 100KHz			-113	dBc/Hz
	input phase noise at 1MHz			-113	dBc/Hz
	input phase noise at 10MHz			-113	dBc/Hz
50MHz	Frequency Tolerance	-50		50	ppm
	Rise / Fall Time			5	ns
	Jitter Tolerance (Accumulated over 100,000 cycles)			1.75	ns
	Duty Cycle	40		60	%
	input phase noise at 1KHz			-87	dBc/Hz
	input phase noise at 10KHz			-107	dBc/Hz
	input phase noise at 100KHz			-107	dBc/Hz
	input phase noise at 1MHz			-107	dBc/Hz
	input phase noise at 10MHz			-107	dBc/Hz
LATENCY TIMING
Tx	Slave RMII Rising edge XI clock with assertion TX_EN to SSD symbol on MDI (100M)		105		ns
	Master RMII Rising edge clock with assertion TX_EN to SSD symbol on MDI (100M)		105		ns
	Slave RMII Rising edge XI clock with assertion TX_EN to SSD symbol on MDI (10M)		1350		ns
	Master RMII Rising edge clock with assertion TX_EN to SSD symbol on MDI (10M)		1300		ns
Rx	SSD symbol on MDI to Slave RMII Rising edge of XI clock with assertion of CRS_DV (100M)		350		ns
	SSD symbol on MDI to Master RMII Rising edge of Master clock with assertion of CRS_DV (100M)		325		ns
	SSD symbol on MDI to Slave RMII Rising edge of XI clock with assertion of CRS_DV (10M)		2150		ns
	SSD symbol on MDI to Master RMII Rising edge of Master clock with assertion of CRS_DV (10M)		2150		ns

(1) Clock shall be available at power ramp. If Clock is provided after power ramp, external Reset of PHY is needed once clock is available

(2) RMII Slave Output Timing default supports setup time upto 7.5 ns. For 7.5ns to 10.5ns, program register 0x0017.8 = 1, 0x0042=0x0014