8.6.89 Register_0x4d2 Register (Offset = 0x4D2) [reset = 0x354A]
Register_0x4d2 is shown in Table 101.
Return to Summary Table.
Table 101. Register_0x4d2 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
15-14 |
cfg_flush_ph_shift_updn |
R/W |
0x0 |
PI_CTRL Register
|
13 |
cfg_ph_shift_toggle_en |
R/W |
0x1 |
PI_CTRL Register
|
12 |
cfg_fast_slave_wake_100 |
R/W |
0x1 |
DSP_100M_EEE_LINK CTRL register
|
11 |
cfg_dis_dscr_100_tout |
R/W |
0x0 |
DSP_100M_EEE_LINK CTRL register
|
10 |
cfg_lpi_pre_flush_en |
R/W |
0x1 |
DSP_EEE_SEQ CTRL register
|
9-5 |
cfg_100m_rx_lpi_ts_timer |
R/W |
0xA |
DSP_100M_EEE_LINK CTRL register
|
4-0 |
cfg_100m_rx_lpi_link_fail |
R/W |
0xA |
DSP_100M_EEE_LINK CTRL register
|