JAJSGP5A December   2018  – August 2019 DP83825I

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      DP83825I アプリケーション図
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     DP83825I Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Auto-Negotiation (Speed / Duplex Selection)
      2. 8.3.2  Auto-MDIX Resolution
      3. 8.3.3  Energy Efficient Ethernet
        1. 8.3.3.1 EEE Overview
        2. 8.3.3.2 EEE Negotiation
      4. 8.3.4  EEE for Legacy MACs Not Supporting 802.3az
      5. 8.3.5  Wake-on-LAN Packet Detection
        1. 8.3.5.1 Magic Packet Structure
        2. 8.3.5.2 Magic Packet Example
        3. 8.3.5.3 Wake-on-LAN Configuration and Status
      6. 8.3.6  Low Power Modes
        1. 8.3.6.1 Active Sleep
      7. 8.3.7  IEEE Power Down
      8. 8.3.8  Deep Power Down
      9. 8.3.9  RMII Repeater Mode
      10. 8.3.10 Reduced Media Independent Interface (RMII)
      11. 8.3.11 Serial Management Interface
        1. 8.3.11.1 Extended Register Space Access
        2. 8.3.11.2 Write Address Operation
        3. 8.3.11.3 Read Address Operation
        4. 8.3.11.4 Write (No Post Increment) Operation
        5. 8.3.11.5 Read (No Post Increment) Operation
        6. 8.3.11.6 Write (Post Increment) Operation
        7. 8.3.11.7 Read (Post Increment) Operation
        8. 8.3.11.8 Example Write Operation (No Post Increment)
        9. 8.3.11.9 Example Read Operation (No Post Increment)
      12. 8.3.12 100BASE-TX
        1. 8.3.12.1 100BASE-TX Transmitter
          1. 8.3.12.1.1 Code-Group Encoding and Injection
          2. 8.3.12.1.2 Scrambler
          3. 8.3.12.1.3 NRZ to NRZI Encoder
          4. 8.3.12.1.4 Binary to MLT-3 Converter
        2. 8.3.12.2 100BASE-TX Receiver
      13. 8.3.13 10BASE-Te
        1. 8.3.13.1 Squelch
        2. 8.3.13.2 Normal Link Pulse Detection and Generation
        3. 8.3.13.3 Jabber
        4. 8.3.13.4 Active Link Polarity Detection and Correction
      14. 8.3.14 Loopback Modes
        1. 8.3.14.1 Near-End Loopback
        2. 8.3.14.2 MII Loopback
        3. 8.3.14.3 PCS Loopback
        4. 8.3.14.4 Digital Loopback
        5. 8.3.14.5 Analog Loopback
        6. 8.3.14.6 Far-End (Reverse) Loopback
      15. 8.3.15 BIST Configurations
      16. 8.3.16 Cable Diagnostics
        1. 8.3.16.1 TDR
        2. 8.3.16.2 Fast Link Down Functionality
      17. 8.3.17 Single Voltage Supply
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Straps Configuration
        1. 8.5.1.1 Straps for PHY Address
    6. 8.6 Register Maps
      1. 8.6.1  BMCR_Register Register (Offset = 0x0) [reset = 0x3100]
        1. Table 13. BMCR_Register Register Field Descriptions
      2. 8.6.2  BMSR_Register Register (Offset = 0x1) [reset = 0x7849]
        1. Table 14. BMSR_Register Register Field Descriptions
      3. 8.6.3  PHYIDR1_Register Register (Offset = 0x2) [reset = 0x2000]
        1. Table 15. PHYIDR1_Register Register Field Descriptions
      4. 8.6.4  PHYIDR2_Register Register (Offset = 0x3) [reset = 0xA140]
        1. Table 16. PHYIDR2_Register Register Field Descriptions
      5. 8.6.5  ANAR_Register Register (Offset = 0x4) [reset = 0x1E1]
        1. Table 17. ANAR_Register Register Field Descriptions
      6. 8.6.6  ALNPAR_Register Register (Offset = 0x5) [reset = 0x0]
        1. Table 18. ALNPAR_Register Register Field Descriptions
      7. 8.6.7  ANER_Register Register (Offset = 0x6) [reset = 0x4]
        1. Table 19. ANER_Register Register Field Descriptions
      8. 8.6.8  ANNPTR_Register Register (Offset = 0x7) [reset = 0x2001]
        1. Table 20. ANNPTR_Register Register Field Descriptions
      9. 8.6.9  ANLNPTR_Register Register (Offset = 0x8) [reset = 0x0]
        1. Table 21. ANLNPTR_Register Register Field Descriptions
      10. 8.6.10 CR1_Register Register (Offset = 0x9) [reset = 0x0]
        1. Table 22. CR1_Register Register Field Descriptions
      11. 8.6.11 CR2_Register Register (Offset = 0xA) [reset = 0x0]
        1. Table 23. CR2_Register Register Field Descriptions
      12. 8.6.12 CR3_Register Register (Offset = 0xB) [reset = 0x0]
        1. Table 24. CR3_Register Register Field Descriptions
      13. 8.6.13 Register_12 Register (Offset = 0xC) [reset = 0x0]
        1. Table 25. Register_12 Register Field Descriptions
      14. 8.6.14 REGCR_Register Register (Offset = 0xD) [reset = 0x0]
        1. Table 26. REGCR_Register Register Field Descriptions
      15. 8.6.15 ADDAR_Register Register (Offset = 0xE) [reset = 0x0]
        1. Table 27. ADDAR_Register Register Field Descriptions
      16. 8.6.16 FLDS_Register Register (Offset = 0xF) [reset = 0x0]
        1. Table 28. FLDS_Register Register Field Descriptions
      17. 8.6.17 PHYSTS_Register Register (Offset = 0x10) [reset = 0x0]
        1. Table 29. PHYSTS_Register Register Field Descriptions
      18. 8.6.18 PHYSCR_Register Register (Offset = 0x11) [reset = 0x108]
        1. Table 30. PHYSCR_Register Register Field Descriptions
      19. 8.6.19 MISR1_Register Register (Offset = 0x12) [reset = 0x0]
        1. Table 31. MISR1_Register Register Field Descriptions
      20. 8.6.20 MISR2_Register Register (Offset = 0x13) [reset = 0x0]
        1. Table 32. MISR2_Register Register Field Descriptions
      21. 8.6.21 FCSCR_Register Register (Offset = 0x14) [reset = 0x0]
        1. Table 33. FCSCR_Register Register Field Descriptions
      22. 8.6.22 RECR_Register Register (Offset = 0x15) [reset = 0x0]
        1. Table 34. RECR_Register Register Field Descriptions
      23. 8.6.23 BISCR_Register Register (Offset = 0x16) [reset = 0x100]
        1. Table 35. BISCR_Register Register Field Descriptions
      24. 8.6.24 RCSR_Register Register (Offset = 0x17) [reset = 0x1]
        1. Table 36. RCSR_Register Register Field Descriptions
      25. 8.6.25 LEDCR_Register Register (Offset = 0x18) [reset = 0x400]
        1. Table 37. LEDCR_Register Register Field Descriptions
      26. 8.6.26 PHYCR_Register Register (Offset = 0x19) [reset = 0x8000]
        1. Table 38. PHYCR_Register Register Field Descriptions
      27. 8.6.27 10BTSCR_Register Register (Offset = 0x1A) [reset = 0x0]
        1. Table 39. 10BTSCR_Register Register Field Descriptions
      28. 8.6.28 BICSR1_Register Register (Offset = 0x1B) [reset = 0x7D]
        1. Table 40. BICSR1_Register Register Field Descriptions
      29. 8.6.29 BICSR2_Register Register (Offset = 0x1C) [reset = 0x5EE]
        1. Table 41. BICSR2_Register Register Field Descriptions
      30. 8.6.30 CDCR_Register Register (Offset = 0x1E) [reset = 0x0]
        1. Table 42. CDCR_Register Register Field Descriptions
      31. 8.6.31 PHYRCR_Register Register (Offset = 0x1F) [reset = 0x0]
        1. Table 43. PHYRCR_Register Register Field Descriptions
      32. 8.6.32 MLEDCR_Register Register (Offset = 0x25) [reset = 0x41]
        1. Table 44. MLEDCR_Register Register Field Descriptions
      33. 8.6.33 COMPT_Regsiter Register (Offset = 0x27) [reset = 0x0]
        1. Table 45. COMPT_Regsiter Register Field Descriptions
      34. 8.6.34 Register_101 Register (Offset = 0x101) [reset = 0x2082]
        1. Table 46. Register_101 Register Field Descriptions
      35. 8.6.35 Register_10a Register (Offset = 0x10A) [reset = 0x2040]
        1. Table 47. Register_10a Register Field Descriptions
      36. 8.6.36 Register_123 Register (Offset = 0x123) [reset = 0x51C]
        1. Table 48. Register_123 Register Field Descriptions
      37. 8.6.37 Register_130 Register (Offset = 0x130) [reset = 0x4F28]
        1. Table 49. Register_130 Register Field Descriptions
      38. 8.6.38 CDSCR_Register Register (Offset = 0x170) [reset = 0x410]
        1. Table 50. CDSCR_Register Register Field Descriptions
      39. 8.6.39 CDSCR2_Register Register (Offset = 0x171) [reset = 0x0]
        1. Table 51. CDSCR2_Register Register Field Descriptions
      40. 8.6.40 TDR_172_Register Register (Offset = 0x172) [reset = 0x0]
        1. Table 52. TDR_172_Register Register Field Descriptions
      41. 8.6.41 CDSCR3_Register Register (Offset = 0x173) [reset = 0x1304]
        1. Table 53. CDSCR3_Register Register Field Descriptions
      42. 8.6.42 TDR_174_Register Register (Offset = 0x174) [reset = 0x0]
        1. Table 54. TDR_174_Register Register Field Descriptions
      43. 8.6.43 TDR_175_Register Register (Offset = 0x175) [reset = 0x1004]
        1. Table 55. TDR_175_Register Register Field Descriptions
      44. 8.6.44 TDR_176_Register Register (Offset = 0x176) [reset = 0x5]
        1. Table 56. TDR_176_Register Register Field Descriptions
      45. 8.6.45 CDSCR4_Register Register (Offset = 0x177) [reset = 0x1E00]
        1. Table 57. CDSCR4_Register Register Field Descriptions
      46. 8.6.46 TDR_178_Register Register (Offset = 0x178) [reset = 0x2]
        1. Table 58. TDR_178_Register Register Field Descriptions
      47. 8.6.47 CDLRR1_Register Register (Offset = 0x180) [reset = 0x0]
        1. Table 59. CDLRR1_Register Register Field Descriptions
      48. 8.6.48 CDLRR2_Register Register (Offset = 0x181) [reset = 0x0]
        1. Table 60. CDLRR2_Register Register Field Descriptions
      49. 8.6.49 CDLRR3_Register Register (Offset = 0x182) [reset = 0x0]
        1. Table 61. CDLRR3_Register Register Field Descriptions
      50. 8.6.50 CDLRR4_Register Register (Offset = 0x183) [reset = 0x0]
        1. Table 62. CDLRR4_Register Register Field Descriptions
      51. 8.6.51 CDLRR5_Register Register (Offset = 0x184) [reset = 0x0]
        1. Table 63. CDLRR5_Register Register Field Descriptions
      52. 8.6.52 CDLAR1_Register Register (Offset = 0x185) [reset = 0x0]
        1. Table 64. CDLAR1_Register Register Field Descriptions
      53. 8.6.53 CDLAR2_Register Register (Offset = 0x186) [reset = 0x0]
        1. Table 65. CDLAR2_Register Register Field Descriptions
      54. 8.6.54 CDLAR3_Register Register (Offset = 0x187) [reset = 0x0]
        1. Table 66. CDLAR3_Register Register Field Descriptions
      55. 8.6.55 CDLAR4_Register Register (Offset = 0x188) [reset = 0x0]
        1. Table 67. CDLAR4_Register Register Field Descriptions
      56. 8.6.56 CDLAR5_Register Register (Offset = 0x189) [reset = 0x0]
        1. Table 68. CDLAR5_Register Register Field Descriptions
      57. 8.6.57 CDLAR6_Register Register (Offset = 0x18A) [reset = 0x0]
        1. Table 69. CDLAR6_Register Register Field Descriptions
      58. 8.6.58 IO_CFG_Register Register (Offset = 0x302) [reset = 0x0]
        1. Table 70. IO_CFG_Register Register Field Descriptions
      59. 8.6.59 SPARE_OUT Register (Offset = 0x308) [reset = 0x2]
        1. Table 71. SPARE_OUT Register Field Descriptions
      60. 8.6.60 DAC_CFG_0 Register (Offset = 0x30B) [reset = 0xC00]
        1. Table 72. DAC_CFG_0 Register Field Descriptions
      61. 8.6.61 DAC_CFG_1 Register (Offset = 0x30C) [reset = 0x20]
        1. Table 73. DAC_CFG_1 Register Field Descriptions
      62. 8.6.62 DSP_CFG_0 Register (Offset = 0x30F) [reset = 0x464]
        1. Table 74. DSP_CFG_0 Register Field Descriptions
      63. 8.6.63 DSP_CFG_2 Register (Offset = 0x311) [reset = 0x1FC]
        1. Table 75. DSP_CFG_2 Register Field Descriptions
      64. 8.6.64 DSP_CFG_4 Register (Offset = 0x313) [reset = 0x6F8]
        1. Table 76. DSP_CFG_4 Register Field Descriptions
      65. 8.6.65 DSP_CFG_13 Register (Offset = 0x31C) [reset = 0x1101]
        1. Table 77. DSP_CFG_13 Register Field Descriptions
      66. 8.6.66 DSP_CFG_16 Register (Offset = 0x31F) [reset = 0xFC36]
        1. Table 78. DSP_CFG_16 Register Field Descriptions
      67. 8.6.67 DSP_CFG_25 Register (Offset = 0x33C) [reset = 0xEC00]
        1. Table 79. DSP_CFG_25 Register Field Descriptions
      68. 8.6.68 DSP_CFG_27 Register (Offset = 0x33E) [reset = 0x261E]
        1. Table 80. DSP_CFG_27 Register Field Descriptions
      69. 8.6.69 ANA_LD_PROG_SL_Register Register (Offset = 0x404) [reset = 0x80]
        1. Table 81. ANA_LD_PROG_SL_Register Register Field Descriptions
      70. 8.6.70 ANA_RX10BT_CTRL_Register Register (Offset = 0x40D) [reset = 0x0]
        1. Table 82. ANA_RX10BT_CTRL_Register Register Field Descriptions
      71. 8.6.71 Register_416 Register (Offset = 0x416) [reset = 0x830]
        1. Table 83. Register_416 Register Field Descriptions
      72. 8.6.72 Register_429 Register (Offset = 0x429) [reset = 0x0]
        1. Table 84. Register_429 Register Field Descriptions
      73. 8.6.73 GENCFG_Register Register (Offset = 0x456) [reset = 0x8]
        1. Table 85. GENCFG_Register Register Field Descriptions
      74. 8.6.74 LEDCFG_Register Register (Offset = 0x460) [reset = 0x10]
        1. Table 86. LEDCFG_Register Register Field Descriptions
      75. 8.6.75 IOCTRL_Register Register (Offset = 0x461) [reset = 0x0]
        1. Table 87. IOCTRL_Register Register Field Descriptions
      76. 8.6.76 SOR1_Register Register (Offset = 0x467) [reset = 0x101]
        1. Table 88. SOR1_Register Register Field Descriptions
      77. 8.6.77 SOR2_Register Register (Offset = 0x468) [reset = 0x80]
        1. Table 89. SOR2_Register Register Field Descriptions
      78. 8.6.78 Register_0x469_Register Register (Offset = 0x469) [reset = 0x40]
        1. Table 90. Register_0x469_Register Register Field Descriptions
      79. 8.6.79 RXFCFG_Register Register (Offset = 0x4A0) [reset = 0x1081]
        1. Table 91. RXFCFG_Register Register Field Descriptions
      80. 8.6.80 RXFS_Register Register (Offset = 0x4A1) [reset = 0x1000]
        1. Table 92. RXFS_Register Register Field Descriptions
      81. 8.6.81 RXFPMD1_Register Register (Offset = 0x4A2) [reset = 0x0]
        1. Table 93. RXFPMD1_Register Register Field Descriptions
      82. 8.6.82 RXFPMD2_Register Register (Offset = 0x4A3) [reset = 0x0]
        1. Table 94. RXFPMD2_Register Register Field Descriptions
      83. 8.6.83 RXFPMD3_Register Register (Offset = 0x4A4) [reset = 0x0]
        1. Table 95. RXFPMD3_Register Register Field Descriptions
      84. 8.6.84 Register_0x4cd Register (Offset = 0x4CD) [reset = 0x408]
        1. Table 96. Register_0x4cd Register Field Descriptions
      85. 8.6.85 Register_0x4ce Register (Offset = 0x4CE) [reset = 0x12]
        1. Table 97. Register_0x4ce Register Field Descriptions
      86. 8.6.86 Register_0x4cf Register (Offset = 0x4CF) [reset = 0x261D]
        1. Table 98. Register_0x4cf Register Field Descriptions
      87. 8.6.87 EEECFG2_Register Register (Offset = 0x4D0) [reset = 0x0]
        1. Table 99. EEECFG2_Register Register Field Descriptions
      88. 8.6.88 EEECFG3_Register Register (Offset = 0x4D1) [reset = 0x18B]
        1. Table 100. EEECFG3_Register Register Field Descriptions
      89. 8.6.89 Register_0x4d2 Register (Offset = 0x4D2) [reset = 0x354A]
        1. Table 101. Register_0x4d2 Register Field Descriptions
      90. 8.6.90 Register_0x4d4 Register (Offset = 0x4D4) [reset = 0x6633]
        1. Table 102. Register_0x4d4 Register Field Descriptions
      91. 8.6.91 DSP_100M_STEP_2_Register Register (Offset = 0x4D5) [reset = 0x2F1]
        1. Table 103. DSP_100M_STEP_2_Register Register Field Descriptions
      92. 8.6.92 DSP_100M_STEP_3_Register Register (Offset = 0x4D6) [reset = 0x171]
        1. Table 104. DSP_100M_STEP_3_Register Register Field Descriptions
      93. 8.6.93 DSP_100M_STEP_4_Register Register (Offset = 0x4D7) [reset = 0x171]
        1. Table 105. DSP_100M_STEP_4_Register Register Field Descriptions
      94. 8.6.94 MMD3_PCS_CTRL_1_Register Register (Offset = 0x1000) [reset = 0x0]
        1. Table 106. MMD3_PCS_CTRL_1_Register Register Field Descriptions
      95. 8.6.95 MMD3_PCS_STATUS_1 Register (Offset = 0x1001) [reset = 0x40]
        1. Table 107. MMD3_PCS_STATUS_1 Register Field Descriptions
      96. 8.6.96 MMD3_EEE_CAPABILITY_Register Register (Offset = 0x1014) [reset = 0x2]
        1. Table 108. MMD3_EEE_CAPABILITY_Register Register Field Descriptions
      97. 8.6.97 MMD3_WAKE_ERR_CNT_Register Register (Offset = 0x1016) [reset = 0x0]
        1. Table 109. MMD3_WAKE_ERR_CNT_Register Register Field Descriptions
      98. 8.6.98 MMD7_EEE_ADVERTISEMENT_Register Register (Offset = 0x203C) [reset = 0x0]
        1. Table 110. MMD7_EEE_ADVERTISEMENT_Register Register Field Descriptions
      99. 8.6.99 MMD7_EEE_LP_ABILITY_Register Register (Offset = 0x203D) [reset = 0x0]
        1. Table 111. MMD7_EEE_LP_ABILITY_Register Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Clock Requirements
          1. 9.2.1.1.1 Oscillator
          2. 9.2.1.1.2 Crystal
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 RMII Layout Guidelines
        2. 9.2.2.2 MDI Layout Guidelines
        3. 9.2.2.3 TPI Network Circuit
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Transformer Layout
        1. 11.1.3.1 Transformer Recommendations
      4. 11.1.4 Metal Pour
      5. 11.1.5 PCB Layer Stacking
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報
    1. 13.0.1 DP83825I パッケージ図
    2. 13.0.2 DP83825I パッケージ図
    3. 13.0.3 DP83825I パッケージ図

8.3.5 Wake-on-LAN Packet Detection

Wake-on-LAN (WoL) provides a mechanism to detect specific frames and notify the connected controller through either register status change, GPIO indication, or an interrupt flag. The WoL feature within the DP83825I allows for connected devices residing above the Physical Layer to remain in a low power state until frames with the qualifying credentials are detected. Supported WoL frame types include: Magic Packet and Magic Packet with Secure-ON Match. When a qualifying WoL frame is received, the DP83825I WoL logic circuit is able to generate a user-defined event (either pulses or level change) through any of the GPIO pins or a status interrupt flag to inform a connected controller that a wake event has occurred. Additionally, the DP83825I includes a CRC Gate to prevent invalid packets from triggering a wake-up event. The Wake-on-LAN feature includes:

  • Identification of WoL frames in all supported speeds (100BASE-TX and 10BASE-Te).
  • Wake-up interrupt generation upon reception of a WoL frame.
  • CRC error checking of WoL frames to prevent interrupt generation from invalid frames.