JAJSGS3B January   2019  – July 2022 ADS8353-Q1

PRODUCTION DATA  

  1. 1特長
  2. 2アプリケーション
  3. 3概要
  4. 4Revision History
  5. 5Pin Configuration and Functions
  6. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
    9. 6.9 Typical Characteristics
  7. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference
      2. 7.3.2 Analog Inputs
        1. 7.3.2.1 Analog Input: Full-Scale Range Selection
        2. 7.3.2.2 Analog Input: Single-Ended and Pseudo-Differential Configurations
      3. 7.3.3 Transfer Function
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Write to User-Programmable Registers
      3. 7.5.3 Data Read Operation
        1. 7.5.3.1 Reading User-Programmable Registers
        2. 7.5.3.2 Conversion Data Read
          1. 7.5.3.2.1 32-CLK, Dual-SDO Mode (CFR.B11 = 0, CFR.B10 = 0, Default)
          2. 7.5.3.2.2 32-CLK, Single-SDO Mode (CFR.B11 = 0, CFR.B10 = 1)
      4. 7.5.4 Low-Power Modes
        1. 7.5.4.1 STANDBY Mode
        2. 7.5.4.2 Software Power-Down (SPD) Mode
      5. 7.5.5 Frame Abort, Reconversion, or Short-Cycling
    6. 7.6 Register Maps
      1. 7.6.1 ADS8353-Q1 Registers
  8. 8Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Amplifier Selection
      2. 8.1.2 Charge Kickback Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
      1.      Mechanical, Packaging, and Orderable Information
7.5.3.2.1 32-CLK, Dual-SDO Mode (CFR.B11 = 0, CFR.B10 = 0, Default)

The 32-CLK, dual-SDO mode is the default mode supported by the device. This mode can also be selected by writing CFR.B11 = 0 and CFR.B10 = 0.

In this mode, the SDO_A pin outputs the ADC_A conversion result and the SDO_B pin outputs the ADC_B conversion result. Figure 7-6 shows a detailed timing diagram for this mode.

GUID-8370F234-EE63-445E-95E0-561633188EE2-low.gifFigure 7-6 32-CLK, Dual-SDO Mode Timing Diagram

A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A and SDO_B pins. The device converts the sampled analog input during the conversion time (tCONV). SDO_A and SDO_B read 0 during this period. After completing the conversion process, the sample-and-hold circuit returns to sample mode. The device outputs the MSBs of ADC_A and ADC_B on the SDO_A and SDO_B pins, respectively, on the 16th SCLK falling edge. As shown in Table 7-9, the subsequent SCLK falling edges are used to shift out the rest of the bits of the conversion result.

Table 7-9 Data Launch Edge
DEVICE PINS LAUNCH EDGE
CS SCLK CS
↓ ↓1 — ↓15 ↓16 — ↓27 ↓28 ↓29 ↓30 ↓31 ↓32 ... ↑
ADS8353-Q1 SDO-A 0 0 — 0 D15_A — D4_A D3_A D2_A D1_A D0_A 0 ... Hi-Z
SDO-B 0 0 — 0 D15_B — D4_B D3_B D2_B D1_B D0_B 0 ... Hi-Z

In this mode, at least 32 SCLK falling edges must be given to validate the read or write frame. A CS rising edge ends the frame and puts the serial bus into 3-state.

See the Section 6.6 table for timing specifications specific to this serial interface mode.