JAJSGS3B January   2019  – July 2022 ADS8353-Q1

PRODUCTION DATA  

  1. 1特長
  2. 2アプリケーション
  3. 3概要
  4. 4Revision History
  5. 5Pin Configuration and Functions
  6. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
    9. 6.9 Typical Characteristics
  7. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference
      2. 7.3.2 Analog Inputs
        1. 7.3.2.1 Analog Input: Full-Scale Range Selection
        2. 7.3.2.2 Analog Input: Single-Ended and Pseudo-Differential Configurations
      3. 7.3.3 Transfer Function
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Write to User-Programmable Registers
      3. 7.5.3 Data Read Operation
        1. 7.5.3.1 Reading User-Programmable Registers
        2. 7.5.3.2 Conversion Data Read
          1. 7.5.3.2.1 32-CLK, Dual-SDO Mode (CFR.B11 = 0, CFR.B10 = 0, Default)
          2. 7.5.3.2.2 32-CLK, Single-SDO Mode (CFR.B11 = 0, CFR.B10 = 1)
      4. 7.5.4 Low-Power Modes
        1. 7.5.4.1 STANDBY Mode
        2. 7.5.4.2 Software Power-Down (SPD) Mode
      5. 7.5.5 Frame Abort, Reconversion, or Short-Cycling
    6. 7.6 Register Maps
      1. 7.6.1 ADS8353-Q1 Registers
  8. 8Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Amplifier Selection
      2. 8.1.2 Charge Kickback Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
      1.      Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

at AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF = 2.5 V (internal), and fDATA = 600 kSPS (unless otherwise noted); minimum and maximum values at TA = –40°C to 125°C; typical values are at TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Ci Input capacitance In sample mode 40 pF
In hold mode 4
Ilkg Input leakage current 0.1 µA
RESOLUTION
Resolution 16 Bits
DC ACCURACY
NMC No missing codes 16 Bits
INL Integral nonlinearity –4 ±1 4 LSB
DNL Differential nonlinearity ±0.6 LSB
EIO Input offset error –1 ±0.5 1 mV
EIO match ADC_A to ADC_B –1 ±0.5 1 mV
dEIO/dT Input offset thermal drift 1 µV/°C
EG Gain error Referenced to the voltage at REFIO_x –0.1 ±0.05 0.1 %FS
EG match ADC_A to ADC_B –0.1 ±0.05 0.1 %FS
dEG/dT Gain error thermal drift Referenced to the voltage at REFIO_x 1 ppm/°C
AC ACCURACY
SINAD Signal-to-noise + distortion VREF = 2.5 V, VREF input range 80.2 83 dB
VREF = 2.5 V, 2x VREF input range 83.9
VREF = 5 V, VREF input range 88.7
SNR Signal-to-noise ratio VREF = 2.5 V, VREF input range 80.5 83 dB
VREF = 2.5 V, 2x VREF input range 84
VREF = 5 V, VREF input range 89
THD Total harmonic distortion VREF = 2.5 V, VREF input range –100 dB
VREF = 2.5 V, 2x VREF input range –100
VREF = 5 V, VREF input range –100
SFDR Spurious-free dynamic range VREF = 2.5 V, VREF input range 105 dB
VREF = 2.5 V, 2 x VREF input range 105
VREF = 5 V, VREF input range 105
INTERNAL VOLTAGE REFERENCE
VREFOUT Reference output voltage REFDAC_x = 1FFh (default) at 25°C 2.495 2.5 2.505 V
VREF-match VREF_A to VREF_B matching REFDAC_x = 1FFh (default) at 25°C ±1 mV
REFDAC_x resolution(1) 1.1 mV
dVREFOUT/dT Reference voltage temperature drift REFDAC_x = 1FFh (default) at 25°C ±10 ppm/°C
dVREFOUT/dt Long-term stability 1000 hours 150 ppm
RO Internal reference output impedance 1 Ω
IREFOUT Reference output dc current 2 mA
CREFOUT Reference output capacitor 10 µF
tREFON Reference output settling time 8 ms
VOLTAGE REFERENCE INPUT
IREF Average reference input current Per ADC 300 µA
CREF External ceramic reference capacitor 10 µF
Ilkg(dc) DC leakage current ±0.1 µA
SAMPLING DYNAMICS
tA Aperture delay 8 ns
tA match ADC_A to ADC_B 40 ps
tAJIT Aperture jitter 50 ps
DIGITAL INPUTS
VIH High-level input voltage DVDD > 2.3 V 0.7 DVDD DVDD + 0.3 V
DVDD ≤ 2.3 V 0.8 DVDD DVDD + 0.3
VIL Low-level input voltage DVDD > 2.3 V –0.3 0.3 DVDD V
DVDD ≤ 2.3 V –0.3 0.2 DVDD
Input current ±10 nA
DIGITAL OUTPUTS
VOH High-level output voltage IOH = 500-µA source 0.8 DVDD DVDD V
VOL Low-level output voltage IOL = 500-µA sink 0 0.2 DVDD V
POWER SUPPLY
AIDD Analog supply current AVDD = 5 V, fastest throughput internal reference 8.5 10 mA
AVDD = 5 V, fastest throughput external reference(2) 7.5 3.6
AVDD = 5V, no conversion internal reference 5.5 7
AVDD = 5 V, no conversion external reference(2) 4.5
AVDD = 5 V, STANDBY mode internal reference 2.5
AVDD = 5 V, STANDBY mode external reference(2) 1
Power-down mode 10 50 µA
DIDD Digital supply current DVDD = 3.3 V, Cload = 10 pF, fastest throughput 0.5 mA
DVDD = 5 V, Cload = 10 pF, fastest throughput 1
PD Power dissipation (normal operation) AVDD = 5 V, fastest throughput, internal reference 42.5 50 mW
(1) Refer to the Reference section for more details.
(2) With internal reference powered down, CFR.B6 = 0.