JAJSGX5C july   2018  – april 2023 BQ25150

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Device Key Default Settings
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Linear Charger and Power Path
        1. 9.3.1.1 Battery Charging Process
          1. 9.3.1.1.1 Pre-Charge
          2. 9.3.1.1.2 Fast Charge
          3. 9.3.1.1.3 Pre-Charge to Fast Charge Transitions and Charge Current Ramping
          4. 9.3.1.1.4 Termination
        2. 9.3.1.2 JEITA and Battery Temperature Dependent Charging
        3. 9.3.1.3 Input Voltage Based Dynamic Power Management (VINDPM) and Dynamic Power Path Management (DPPM)
        4. 9.3.1.4 Battery Supplement Mode
      2. 9.3.2  Protection Mechanisms
        1. 9.3.2.1 Input Over-Voltage Protection
        2. 9.3.2.2 Safety Timer and I2C Watchdog Timer
        3. 9.3.2.3 Thermal Protection and Thermal Charge Current Foldback
        4. 9.3.2.4 Battery Short and Over Current Protection
        5. 9.3.2.5 PMID Short Circuit
        6. 9.3.2.6 Maximum Allowable Charging Current (IMAX)
      3. 9.3.3  ADC
        1. 9.3.3.1 ADC Operation in Active Battery Mode and Low Power Mode
        2. 9.3.3.2 ADC Operation When VIN Present
        3. 9.3.3.3 ADC Measurements
        4. 9.3.3.4 ADC Programmable Comparators
      4. 9.3.4  VDD LDO
      5. 9.3.5  Load Switch / LDO Output and Control
      6. 9.3.6  PMID Power Control
      7. 9.3.7  MR Wake and Reset Input
        1. 9.3.7.1 MR Wake or Short Button Press Functions
        2. 9.3.7.2 MR Reset or Long Button Press Functions
      8. 9.3.8  14-Second Watchdog for HW Reset
      9. 9.3.9  Faults Conditions and Interrupts ( INT)
        1. 9.3.9.1 Flags and Fault Condition Response
      10. 9.3.10 Power Good ( PG) Pin
      11. 9.3.11 External NTC Monitoring (TS)
        1. 9.3.11.1 TS Thresholds
      12. 9.3.12 External NTC Monitoring (ADCIN)
      13. 9.3.13 I2C Interface
        1. 9.3.13.1 F/S Mode Protocol
    4. 9.4 Device Functional Modes
      1. 9.4.1 Ship Mode
      2. 9.4.2 Low Power
      3. 9.4.3 Active Battery
      4. 9.4.4 Charger/Adapter Mode
      5. 9.4.5 Power-Up/Down Sequencing
    5. 9.5 Register Map
      1. 9.5.1 I2C Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Input (IN/PMID) Capacitors
        2. 10.2.2.2 VDD, LDO Input and Output Capacitors
        3. 10.2.2.3 TS
        4. 10.2.2.4 IMAX Selection
        5. 10.2.2.5 Recommended Passive Components
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 サード・パーティ製品に関する免責事項
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  15. 14Mechanical, Packaging, and Orderable Information

7 Pin Configuration and Functions

GUID-4D943B70-DF3D-45D5-8633-FE7620F5B00D-low.gif Figure 7-1 YFP Package20-Pin DSBGATop View
Table 7-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
IN A1 I DC Input Power Supply. IN is connected to the external DC supply. Bypass IN to GND with at least 1 µF of capacitance using a ceramic capacitor.
PMID A2, B2 I/O High Side Bypass Connection. Connect at least 10-µF ceramic capacitor (at least 3 µF of ceramic capacitance with DC bias de-rating) from PMID to GND as close to the PMID and GND pins as possible. Note: Shorting PMID to IN pin is not recommended as it may cause large discharge current from battery to IN if IN pin is not truly floating.
GND A4 PWR Ground connection. Connect to the ground plane of the circuit.
VDD D1 O Digital supply LDO. Connect at least 4.7-µF capacitor to ground.
CE C2 I Charge Enable. Drive CE low or leave disconnected to enable charging when VIN is valid. Drive CE high to disable charge when VIN is present. CE is pulled low internally with 900-kΩ resistor. CE has no effect when VIN is not present.
SCL E3 I/O I2C Interface Clock. Connect SCL to the logic rail through a 10-kΩ resistor.
SDA E2 I I2C Interface Data. Connect SDA to the logic rail through a 10-kΩ resistor.
LP D3 I Low Power Mode Enable. Drive this pin low to set the device in low power mode when powered by the battery. This pin must be driven high to allow I2C communication when VIN is not present. LP is pulled low internally with 900-kΩ resistor. This pin has no effect when VIN is present.
IMAX C3 I Connect a 10-kΩ or lower resistor to this pin to set the maximum allowable fast charge current. Must not be left floating.
INT D2 O INT is an open-drain output that signals fault interrupts. When a fault occurs, a 128-µs pulse is sent out as an interrupt for the host. INT is enabled/disabled using the MASK_INT bit in the control register.
ADCIN C4 I Input Channel to the ADC. Maximum ADC range 1.2 V. Leave floating or connect to ground if not used.
MR C1 I Manual Reset Input. MR is a general purpose input that must be held low for greater than tHWRESET to go into HW Reset and power cycle the output rails. If MR is also used to wake up the device out of Ship Mode when pressed for at least tWAKE2. MR has in internal 125-kΩ pull-up resistor to BAT.
LS/LDO D4 O Load Switch or LDO output. Connect 2.2 µF of ceramic capacitance to this pin to assure stability. Be sure to account for capacitance bias voltage derating when selecting the capacitor. If LDO is not to be used,, the pin may be shorted to VINLS
VINLS E4 I Input to the Load Switch / LDO output. Connect at least 1 µF of ceramic capacitance from this pin to ground.
BAT A3, B3 I/O Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with at least 1 µF of ceramic capacitance.
TS B4 I Battery Pack NTC Monitor. Connect TS to a 10-kΩ NTC Thermistor in parallel to a 10-kΩ resistor. If TS function is not to be used connect a 5-kΩ resistor from TS to ground.
PG B1 O Open-drain Power Good status indication output. PG is pulled to GND when VIN is above VBAT+ VSLP and less than VOVP. PG is high-impedance when the input power is not within specified limits. Connect PG to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor, or use with an LED for visual indication. PG can also be configured through I2C as a push-button level shifted output ( MR), where the output of the PG pin reflects the status of the MR input, but pulled up to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor. The PG pin can also be configured as a general purpose open drain output.
VIO E1 I System IO supply. Connect to system IO supply to allow level shifting of input signals (SDA, SCL, LP and CE) to the device internal digital domain. Connect to VDD when external IO supply is not available.