JAJSGX9B August   2018  – January 2020 TLV1805-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      N チャネル MOSFET による逆電流保護
      2.      P チャネル MOSFET による逆電流および過電圧保護
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Rail to Rail Inputs
      2. 7.3.2 Power On Reset
      3. 7.3.3 High Power Push-Pull Output
      4. 7.3.4 Shutdown Function
      5. 7.3.5 Internal Hysteresis
    4. 7.4 Device Functional Modes
      1. 7.4.1 External Hysteresis
        1. 7.4.1.1 Inverting Comparator With Hysteresis
        2. 7.4.1.2 Noninverting Comparator With Hysteresis
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
      4. 8.2.4 Reverse Current Protection Using MOSFET and TLV1805-Q1
        1. 8.2.4.1 Minimum Reverse Current
        2. 8.2.4.2 N-Channel Reverse Current Protection Circuit
          1. 8.2.4.2.1 N-Channel Oscillator Circuit
      5. 8.2.5 P-Channel Reverse Current Protection Circuit
      6. 8.2.6 P-Channel Reverse Current Protection With Overvotlage Protection
      7. 8.2.7 ORing MOSFET Controller
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

6.5 Electrical Characteristics

VS = 3.3 V to 40 V, VCM = VS / 2; TA = 25°C (unless otherwise noted). Typical values are at VS = 12 V and TA = 25°C,VCM = VS / 2
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIO Input offset voltage VS = 3.3V, 12V and 40V -4.5 ±0.5 4.5 mV
VS = 3.3V, 12V and 40V, TA = –40°C to +125°C -6.5 6.5
dVIO/dT Input offset voltage drift TA = –40°C to +125°C ±2.5 μV/°C
VHYS Input hysteresis voltage 14 mV
VCM Common-mode voltage range TA = -40℃ to +125℃ (V–) – 0.2 (V+) + 0.2 V
IB Input bias current 0.05 pA
IOS Input offset current 0.05 pA
PSRR Power-supply rejection ratio VCM = V- 95 dB
CMRR Common-mode rejection ratio (V–) < VCM < (V+) 80 dB
VOL Voltage output swing from (V–) ISINK ≤ 5mA, input overdrive = –100 mV,
VS = 5V, TA = –40°C to +125°C 		 300 mV
VOH Voltage output swing from (V+)
 		 ISOURCE ≤ 5mA, input overdrive = +100 mV,
VS = 5V,  TA = –40°C to +125°C		 300 mV
Isc_source Peak charging current (sourcing) with output shorted to V- (1) Vs = 5 V to 40 V 100 mA
Isc_sink Peak dis-charging current (sinking) with output shorted to V+ (1) Vs = 5 V to 40 V 100 mA
IQ Quiescent current VS = 12 V, no load, VID = –0.1 V (output low), TA = 25°C 135 200 µA
VS =12V to 40V no load, VID = –0.1 V (output low), TA = –40°C to +125°C 400 µA
tOFF Time to enter shutdown CL = 15 pF 1.0 µs
tON Time to exit shutdown CL = 15 pF 2.3 µs
VSD Shutdown input: voltage range (2) V s= 3.3 to 40V, TA = -40 to 125 °C 0 5.5 V
VSD_VIH SHDN pin input high level VS = 3.3 V and 40V, TA = -40 to 125 °C 2 1.35 V
VSD_VIL SHDN pin input low level VS = 3.3 V and 40V, TA = -40 to 125 °C 0.65 0.4 V
IB-SDH SHDN bias current VS = VSD = 5.5 V 0.015 nA
VS = 5 V, VSD = 0 V 0.001 nA
IQ-SD Quiescent current (Shutdown) VS = 12V; TS = 25°C; VSD > VSD_VIH Min 9.5 13 µA
(1) Continuous short circuit can result in excessive heating and exceeding the maximum allowed junction temperature of 150°C. Please refer to the Maximum Output Current Derating curve in the Typical Operation Plots.
(2) The recommended voltage range if VSD is independent of VS.