JAJSH23D March   2019  – September 2021 MSP430FR2672 , MSP430FR2673 , MSP430FR2675 , MSP430FR2676

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Types
    6. 7.6 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Active Mode Supply Current Per MHz
    6. 8.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Typical Characteristics – Low-Power Mode Supply Currents
    10. 8.10 Current Consumption Per Module
    11. 8.11 Thermal Resistance Characteristics
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1  Power Supply Sequencing
        1. 8.12.1.1 PMM, SVS and BOR
      2. 8.12.2  Reset Timing
        1. 8.12.2.1 Wake-up Times From Low-Power Modes and Reset
      3. 8.12.3  Clock Specifications
        1. 8.12.3.1 XT1 Crystal Oscillator (Low Frequency)
        2. 8.12.3.2 DCO FLL, Frequency
        3. 8.12.3.3 DCO Frequency
        4. 8.12.3.4 REFO
        5. 8.12.3.5 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. 8.12.3.6 Module Oscillator (MODOSC)
      4. 8.12.4  Digital I/Os
        1. 8.12.4.1 Digital Inputs
        2. 8.12.4.2 Digital Outputs
        3. 8.12.4.3 Typical Characteristics – Outputs at 3 V and 2 V
      5. 8.12.5  Internal Shared Reference
        1. 8.12.5.1 Internal Reference Characteristics
      6. 8.12.6  Timer_A and Timer_B
        1. 8.12.6.1 Timer_A
        2. 8.12.6.2 Timer_B
      7. 8.12.7  eUSCI
        1. 8.12.7.1 eUSCI (UART Mode) Clock Frequency
        2. 8.12.7.2 eUSCI (UART Mode) Timing Characteristics
        3. 8.12.7.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.12.7.4 eUSCI (SPI Master Mode)
        5. 8.12.7.5 eUSCI (SPI Slave Mode)
        6. 8.12.7.6 eUSCI (I2C Mode)
      8. 8.12.8  ADC
        1. 8.12.8.1 ADC, Power Supply and Input Range Conditions
        2. 8.12.8.2 ADC, Timing Parameters
        3. 8.12.8.3 ADC, Linearity Parameters
      9. 8.12.9  Enhanced Comparator (eCOMP)
        1. 8.12.9.1 eCOMP0 Characteristics
      10. 8.12.10 CapTIvate
        1. 8.12.10.1 CapTIvate Electrical Characteristics
        2. 8.12.10.2 CapTIvate Signal-to-Noise Ratio Characteristics
      11. 8.12.11 FRAM
        1. 8.12.11.1 FRAM Characteristics
      12. 8.12.12 Debug and Emulation
        1. 8.12.12.1 JTAG, 4-Wire and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Operating Modes
    4. 9.4  Interrupt Vector Addresses
    5. 9.5  Bootloader (BSL)
    6. 9.6  JTAG Standard Interface
    7. 9.7  Spy-Bi-Wire Interface (SBW)
    8. 9.8  FRAM
    9. 9.9  Memory Protection
    10. 9.10 Peripherals
      1. 9.10.1  Power-Management Module (PMM)
      2. 9.10.2  Clock System (CS) and Clock Distribution
      3. 9.10.3  General-Purpose Input/Output Port (I/O)
      4. 9.10.4  Watchdog Timer (WDT)
      5. 9.10.5  System (SYS) Module
      6. 9.10.6  Cyclic Redundancy Check (CRC)
      7. 9.10.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 9.10.8  Timers (TA0, TA1, TA2, TA3 and TB0)
      9. 9.10.9  Hardware Multiplier (MPY)
      10. 9.10.10 Backup Memory (BAKMEM)
      11. 9.10.11 Real-Time Clock (RTC)
      12. 9.10.12 12-Bit Analog-to-Digital Converter (ADC)
      13. 9.10.13 eCOMP0
      14. 9.10.14 CapTIvate Technology
      15. 9.10.15 Embedded Emulation Module (EEM)
    11. 9.11 Input/Output Diagrams
      1. 9.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.11.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.11.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.11.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.11.5 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      6. 9.11.6 Port P6 (P6.0 to P6.2) Input/Output With Schmitt Trigger
    12. 9.12 Device Descriptors
    13. 9.13 Memory
      1. 9.13.1 Memory Organization
      2. 9.13.2 Peripheral File Map
    14. 9.14 Identification
      1. 9.14.1 Revision Identification
      2. 9.14.2 Device Identification
      3. 9.14.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Layout Guidelines
      2. 10.2.2 CapTIvate Peripheral
        1. 10.2.2.1 Device Connection and Layout Fundamentals
        2. 10.2.2.2 125
        3. 10.2.2.3 Measurements
          1. 10.2.2.3.1 SNR
          2. 10.2.2.3.2 Sensitivity
          3. 10.2.2.3.3 Power
    3. 10.3 CapTIvate Technology Evaluation
  11. 11Device and Documentation Support
    1. 11.1 Getting Started and Next Steps
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Export Control Notice
    9. 11.9 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

8.7 Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETERVCC–40°C25°C85°C105°CUNIT
TYPMAXTYPMAXTYPMAXTYPMAX
ILPM3,XT1Low-power mode 3, 12.5-pF crystal, includes SVS(2)(3)(4)3 V1.21.487.8217.1246µA
2 V1.171.467.7516.99
ILPM3, REFOLow-power mode 3, RTC, excludes SVS(10)3 V1.872.208.5317.76µA
2 V1.852.188.4717.65
ILPM3,VLOLow-power mode 3, VLO, excludes SVS(5)3 V0.921.207.5416.8345.8µA
2 V0.901.177.4716.70
ILPM3, RTCLow-power mode 3, RTC, excludes SVS(9)3 V0.991.277.616.9µA
2 V0.971.247.5316.77
ILPM3, CapTIvate, 1 proximity, wake on touch, XT1Low-power mode 3, CapTIvate , excludes SVS(11)3 V6.1µA
ILPM3, CapTIvate, 1 proximity, wake on touch, REFOLow-power mode 3, CapTIvate , excludes SVS(11)3 V6.9µA
ILPM3, CapTIvate, 1 button, wake on touch, XT1Low-power mode 3, CapTIvate, excludes SVS(12)3 V4.0µA
ILPM3, CapTIvate, 1 button, wake on touch, REFOLow-power mode 3, CapTIvate, excludes SVS(12)3 V4.8µA
ILPM3, CapTIvate, 4 buttons, wake on touch, XT1Low-power mode 3, CapTIvate, excludes SVS(13)3 V4.6µA
ILPM3, CapTIvate, 4 buttons, wake on touch, REFOLow-power mode 3, CapTIvate, excludes SVS(13)3 V5.4µA
ILPM3, CapTIvate, 16 buttons, XT1Low-power mode 3, CapTIvate, excludes SVS(14)3 V33.8µA
ILPM3, CapTIvate, 16 buttons, REFOLow-power mode 3, CapTIvate, excludes SVS(14)3 V34.2µA
ILPM3, CapTIvate, 64 buttons, XT1Low-power mode 3, CapTIvate, excludes SVS(15)3 V145.2µA
ILPM3, CapTIvate, 64 buttons, REFOLow-power mode 3, CapTIvate, excludes SVS(15)3 V144.7µA
ILPM4, SVSLow-power mode 4, includes SVS(6)3 V0.650.907.1916.41µA
2 V0.640.897.1316.30
ILPM4Low-power mode 4, excludes SVS(6)3 V0.500.747.0216.24µA
2 V0.490.736.9616.13
ILPM4,VLOLow-power mode 4, RTC is soured from VLO, excludes SVS(7)3 V0.590.837.1216.35µA
2 V0.580.827.0616.24
ILPM4,XT1Low-power mode 4, RTC is soured from XT1, excludes SVS(8)3 V0.921.27.5416.84µA
2 V0.901.187.4716.70
ILPM4, CapTIvate, 1 proximity, wake on touchLow-power mode 4, CapTIvate, excludes SVS(16)3 V5.5µA
ILPM4, CapTIvate, 1 button, wake on touchLow-power mode 4, CapTIvate, excludes SVS(16)3 V3.4µA
ILPM4, CapTIvate, 4 buttons, wake on touchLow-power mode 4, CapTIvate, excludes SVS(17)3  V3.8µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Not applicable for MCUs with HF crystal oscillator only.
(3) Characterized with a Seiko Crystal SC-32S MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5-pF load.
(4) Low-power mode 3, 12.5-pF crystal, includes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3)
fXT1 = 32768 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
(6) Low-power mode 4, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4), CPU and all clocks are disabled, WDT and RTC disabled
(7) Low-power mode 4, VLO, excludes SVS test conditions:
Current for RTC clocked by VLO included. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4)
fXT1 = 0 Hz, fMCLK = fSMCLK = 0 MHz
(8) Low-power mode 4, XT1, excludes SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4)
fXT1 = 32768 Hz, fMCLK = fSMCLK = 0 MHz
(9) RTC periodically wakes up every second with external 32768-Hz input as source.
(10) RTC periodically wakes up every second with internal REFO 32768-Hz input as source.
(11) CapTIvate technology works in LPM3 with one proximity sensor for wake on touch. CapTIvate BSWP demo panel with 1.5-mm overlay. Current for brownout included. SVS disabled (SVSHE = 0),
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 800, see the specified clock source (XT1 or REFO) condition on each test item.
(12) CapTIvate technology works in LPM3 with one button, wake on touch. CapTIvate BSWP demo panel with 1.5-mm overlay, Current for brownout included. SVS disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250, see the specified clock source (XT1 or REFO) condition on each test item.
(13) CapTIvate technology works in LPM3 with four self-capacitance buttons, wake on touch. CapTIvate BSWP demo panel with 1.5-mm overlay. Current for brownout included. SVS disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250, see the specified clock source (XT1 or REFO) condition on each test item.
(14) CapTIvate technology works in LPM3 with 16 self-capacitance buttons. The CPU enters active mode in between time cycles to configure the conversions and read the results. CapTIvate BSWP demo panel with 1.5-mm overlay. Current for brownout included. SVS disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250, see the specified clock source (XT1 or REFO) condition on each test item.
(15) CapTIvate technology works in LPM3 with 64 mutual-capacitance buttons. The CPU enters active mode in between time cycles to configure the conversions and read the results. CapTIvate BSWP demo panel with 1.5-mm overlay. Current for brownout included. SVS disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 4 MHz, COUNTS = 250, see the specified clock source (XT1 or REFO) condition on each test item.
(16) CapTIvate technology works in LPM4 with one button, wake on touch. CapTIvate BSWP demo panel with 1.5-mm overlay, Current for brownout included. SVS disabled (SVSHE = 0).VLO (10 kHz) sources to CapTIvate timer, no external crystal.
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250
(17) CapTIvate technology works in LPM4 with four self-capacitance buttons, wake on touch. CapTIvate BSWP demo panel with 1.5-mm overlay. Current for brownout included. SVS disabled (SVSHE = 0). VLO (10 kHz) sources to CapTIvate timer, no external crystal.
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250