JAJSH25B March   2019  – August 2019 LMK00804B-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. Table 1. Absolute Maximum Ratings
    2. Table 2. ESD Ratings
    3. Table 3. Recommended Operating Conditions
    4. Table 4. Thermal Information
    5. Table 5. Power Supply Characteristics
    6. Table 6. LVCMOS / LVTTL DC Electrical Characteristics
    7. Table 7. Differential Input DC Electrical Characteristics
    8. Table 8. Switching Characteristics
    9. Table 9. Pin Characteristics
    10. 6.1      Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clock Enable Timing
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Output Clock Interface Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
          1. 9.2.1.3.1 System-Level Phase Noise and Additive Jitter Measurement
      2. 9.2.2 Input Detail
      3. 9.2.3 Input Clock Interface Circuits
    3. 9.3 Do's and Don'ts
      1. 9.3.1 Power Dissipation Calculations
      2. 9.3.2 Thermal Management
      3. 9.3.3 Recommendations for Unused Input and Output Pins
      4. 9.3.4 Input Slew Rate Considerations
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Considerations
      1. 10.1.1 Power-Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground Planes
      2. 11.1.2 Power Supply Pins
      3. 11.1.3 Differential Input Termination
      4. 11.1.4 LVCMOS Input Termination
      5. 11.1.5 Output Termination
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

Table 6. LVCMOS / LVTTL DC Electrical Characteristics

VDD = 3.3 V ± 5%, VDDO = 1.5 V ± 5%, 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = –40°C to 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH Input high voltage CLK_EN,
CLK_SEL		 2 VDD + 0.3 V
LVCMOS_CLK 2 VDD + 0.3 V
VIL Input low voltage CLK_EN,
CLK_SEL		 –0.3 0.8 V
LVCMOS_CLK –0.3 1.3
IIH Input high current CLK_EN,
CLK_SEL		 VIH = VDD 15 µA
LVCMOS_CLK VDD = 3.465 V,
VIN = 3.465 V		 150
IIL Input low current CLK_EN,
CLK_SEL		 VIL = GND –150 µA
LVCMOS_CLK VDD = 3.465 V,
VIN = 0 V		 –150
VOH Output high voltage(1) VDDO = 3.3 V ± 5% 2.64 V
VDDO = 2.5 V ± 5% 2
VDDO = 1.8 V ± 5% 1.44
VDDO = 1.5 V ± 5% 1.2
VOL Output low voltage(1) VDDO = 3.3 V ± 5% 0.66 V
VDDO = 2.5 V ± 5% 0.5
VDDO = 1.8 V ± 5% 0.36
VDDO = 1.5 V ± 5% 0.3
IOZL Output Hi-Z current low –5 µA
IOZH Output Hi-Z current high 5
(1) Outputs terminated with 50 Ω to VDDO/2.