JAJSH94 データシート

JAJSH94 April 2019 BQ79606A-Q1

PRODUCTION DATA.

8.3.5 Cell Balancing

The BQ79606A-Q1 integrates a MOSFET for each cell to enable passive balancing with a minimum of external components. Passive cell balancing slowly discharges individual higher voltage cells to balance the voltage across all of the cells in the stack. Cell balancing reduces the aging rate differences between cells to extend the battery pack overall lifetime. The drawback to passive balancing is heat generation. The energy during discharge is dissipated across an external resistor generating heat. The cell balancing current must be chosen as a tradeoff between the time it takes to balance and the heat generated in the process. The cell balancing algorithm is fully configurable and runs autonomously once enabled. Cell balancing is terminated either when the individual timer expires, or the cell voltage reaches a programmed threshold.

External resistors set the cell balancing current. Figure 18 illustrates the circuit and current flow during balancing. Cell balancing is available with a CBDONE comparator function for cell voltages greater than 2.8V. ADC reads are available during cell balancing. Cell balancing sequencing is programmable to balance cells in two banks, the odd cells and the even cells. Additionally, a cell balancing comparator is integrated that monitors the cell voltages and terminates cell balancing once the voltage V_CBDONE threshold is reached. The cell balancing time is programmable for each individual cell. Additionally, a duty cycle timing function is built into the BQ79606A-Q1 to switch between banks during balancing to achieve a simultaneous stack balance. Using these timing features, the host microcontroller controls the specific algorithm used for cell balancing.

While active, the status of the individual cell balancing switch is indicated in the CB_SW_STAT register. As the cell balancing for each cell completes, the CB_DONE register is updated. When the timer or voltage is satisfied for a particular cell, the switch is disabled and the corresponding CB_DONE[CELL*] bit is set.

NOTE

The CB pins must NEVER be connected to cell voltages (module connectors) that are expected to be negative. The internal FET diode will conduct and likely damage the FET in reverse voltage conditions.

Figure 18. Cell Balancing Circuit