JAJSH94 データシート

JAJSH94 April 2019 BQ79606A-Q1

PRODUCTION DATA.

8.3.5.1.3 Cell Balance Sequencing

Once all of the parameters are set and the sequencing is selected, write the CONTROL2[BAL_GO] bit to 1 to start the cell balancing. When the BAL_GO bit is set, all of the configuration registers are sampled. Any changes to the configuration registers are ignored during the balancing cycle. A second BAL_GO must be performed to change any settings. Once enabled, balancing proceeds according to the flowchart in Figure 19. The DEV_STAT[CB_RUN] bit is set for the entire cell balancing cycle, regardless if paused. It is cleared once the DEV_STAT[CB_DONE] bit is set.

During non-duty cycle operation CB_CONFIG[DUTY]=00, when an individual cell's balancing timer expires or the voltage falls to the programmed threshold, the balancing FET for that cell is disabled, the CB_DONE[CELL*] bit is set for that cell, and any cells with remaining time continue to balance. Once all of the selected bank of cells have completed balancing (either by timer expiration or voltage), the second bank (if selected) are balanced using the same procedure. Once all of the cells in that bank are balanced, the DEV_STAT[CB_DONE] bit is set, indicating that balancing is complete. The host is not required to monitor the balancing once the CONTROL2[BAL_GO] bit is set, allowing the host to enter a low power mode. Note that when cell balancing is disabled for a cell that is in a bank to be balanced (by setting the timer to 0), the corresponding CB_DONE[CELL*] bit is set immediately after the BAL_GO bit is set. When only balancing even or odd cells (CB_CONFIG[SEQ] = 0b00 or 0b01), only the bank that is balanced updates the CB_DONE[CELL*] bits. The CB_DONE[CELL*] bits for the non-balanced bank of cells are reset with the BAL_GO command, but are not modified during the balancing operation. For instance, after a completed cell balancing cycle where only the odd cells are balanced, the CB_DONE register reads (assuming no faults during the cell balancing) 0x15.

With duty cycle operation enabled (CB_CONFIG[DUTY] ≠00), the sequence follows the CB_CONFIG[SEQ] programming. The duty cycle timer runs in parallel with the cell timers. The odd or even cell balancing runs for the time programmed in CB_CONFIG[DUTY] and CB_CONFIG[DUTY_UNIT] and then switches to the other bank for the programmed time. The process continues switching back and forth until all of the cells are balanced. If all cells in a particular bank have completed, while some remain in the second bank, the device does not switch to the completed bank and, instead remains on the unfinished bank until all cells complete.

Cell balancing is paused using the CB_SW_EN[CB_PAUSE] bit. When set, the cell balancing state machine is frozen and all switches are turned off and the DEV_STAT[CB_PAUSE] bit is set. Cell balancing must be paused before doing diagnostics. If a fault occurs while cell balancing is in the pause state, nothing happens to the cell balancing logic, regardless of the state of the CB_CONFIG[FLTSTOP] bit. If the fault exists when the CB_PAUSE bit is cleared, the cell balancing takes action at that point based on the state of the FLTSTOP bit.

NOTE

The CB_CONFIG[DUTY_UNIT] and the CB_CELL1_CTRL[TIME_UNIT] unit must be the same. If minutes is selected for CB_CONFIG[DUTY_UNIT] minutes must be selected for CB_CELL1_CTRL[TIME_UNIT] as well.

Figure 19. Flow Diagram for Cell Balancing