JAJSHC8B
May 2019 – October 2019
TLV320ADC3140
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
ブロック概略図
4
改訂履歴
5
概要(続き)
6
デバイス比較表
7
Pin Configuration and Functions
Pin Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing Requirements: I2C Interface
8.7
Switching Characteristics: I2C Interface
8.8
Timing Requirements: SPI Interface
8.9
Switching Characteristics: SPI Interface
8.10
Timing Requirements: TDM, I2S or LJ Interface
8.11
Switching Characteristics: TDM, I2S or LJ Interface
8.12
Timing Requirements: PDM Digital Microphone Interface
8.13
Switching Characteristics: PDM Digial Microphone Interface
8.14
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Serial Interfaces
9.3.1.1
Control Serial Interfaces
9.3.1.2
Audio Serial Interfaces
9.3.1.2.1
Time Division Multiplexed Audio (TDM) Interface
9.3.1.2.2
Inter IC Sound (I2S) Interface
9.3.1.2.3
Left-Justified (LJ) Interface
9.3.1.3
Using Multiple Devices With Shared Buses
9.3.2
Phase-Locked Loop (PLL) and Clock Generation
9.3.3
Input Channel Configurations
9.3.4
Reference Voltage
9.3.5
Programmable Microphone Bias
9.3.6
Signal-Chain Processing
9.3.6.1
Programmable Channel Gain and Digital Volume Control
9.3.6.2
Programmable Channel Gain Calibration
9.3.6.3
Programmable Channel Phase Calibration
9.3.6.4
Programmable Digital High-Pass Filter
9.3.6.5
Programmable Digital Biquad Filters
9.3.6.6
Programmable Channel Summer and Digital Mixer
9.3.6.7
Configurable Digital Decimation Filters
9.3.6.7.1
Linear Phase Filters
9.3.6.7.1.1
Sampling Rate: 8 kHz or 7.35 kHz
9.3.6.7.1.2
Sampling Rate: 16 kHz or 14.7 kHz
9.3.6.7.1.3
Sampling Rate: 24 kHz or 22.05 kHz
9.3.6.7.1.4
Sampling Rate: 32 kHz or 29.4 kHz
9.3.6.7.1.5
Sampling Rate: 48 kHz or 44.1 kHz
9.3.6.7.1.6
Sampling Rate: 96 kHz or 88.2 kHz
9.3.6.7.1.7
Sampling Rate: 192 kHz or 176.4 kHz
9.3.6.7.1.8
Sampling Rate: 384 kHz or 352.8 kHz
9.3.6.7.1.9
Sampling Rate 768 kHz or 705.6 kHz
9.3.6.7.2
Low-Latency Filters
9.3.6.7.2.1
Sampling Rate: 16 kHz or 14.7 kHz
9.3.6.7.2.2
Sampling Rate: 24 kHz or 22.05 kHz
9.3.6.7.2.3
Sampling Rate: 32 kHz or 29.4 kHz
9.3.6.7.2.4
Sampling Rate: 48 kHz or 44.1 kHz
9.3.6.7.2.5
Sampling Rate: 96 kHz or 88.2 kHz
9.3.6.7.2.6
Sampling Rate 192 kHz or 176.4 kHz
9.3.6.7.3
Ultra-Low-Latency Filters
9.3.6.7.3.1
Sampling Rate: 16 kHz or 14.7 kHz
9.3.6.7.3.2
Sampling Rate: 24 kHz or 22.05 kHz
9.3.6.7.3.3
Sampling Rate: 32 kHz or 29.4 kHz
9.3.6.7.3.4
Sampling Rate: 48 kHz or 44.1 kHz
9.3.6.7.3.5
Sampling Rate: 96 kHz or 88.2 kHz
9.3.6.7.3.6
Sampling Rate 192 kHz or 176.4 kHz
9.3.6.7.3.7
Sampling Rate 384 kHz or 352.8 kHz
9.3.7
Automatic Gain Controller (AGC)
9.3.8
Digital PDM Microphone Record Channel
9.3.9
Interrupts, Status, and Digital I/O Pin Multiplexing
9.4
Device Functional Modes
9.4.1
Hardware Shutdown
9.4.2
Sleep Mode or Software Shutdown
9.4.3
Active Mode
9.4.4
Software Reset
9.5
Programming
9.5.1
Control Serial Interfaces
9.5.1.1
I2C Control Interface
9.5.1.1.1
General I2C Operation
9.5.1.1.2
I2C Single-Byte and Multiple-Byte Transfers
9.5.1.1.2.1
I2C Single-Byte Write
9.5.1.1.2.2
I2C Multiple-Byte Write
9.5.1.1.2.3
I2C Single-Byte Read
9.5.1.1.2.4
I2C Multiple-Byte Read
9.5.1.2
SPI Control Interface
Table 1.
SPI Command Word
9.6
Register Maps
9.6.1
Device Configuration Registers
9.6.1.1
Register Descriptions
9.6.1.1.1
PAGE_CFG Register (page = 0x00, address = 0x00) [reset = 0h]
Table 51.
PAGE_CFG Register Field Descriptions
9.6.1.1.2
SW_RESET Register (page = 0x00, address = 0x01) [reset = 0h]
Table 52.
SW_RESET Register Field Descriptions
9.6.1.1.3
SLEEP_CFG Register (page = 0x00, address = 0x02) [reset = 0h]
Table 53.
SLEEP_CFG Register Field Descriptions
9.6.1.1.4
SHDN_CFG Register (page = 0x00, address = 0x05) [reset = 5h]
Table 54.
SHDN_CFG Register Field Descriptions
9.6.1.1.5
ASI_CFG0 Register (page = 0x00, address = 0x07) [reset = 30h]
Table 55.
ASI_CFG0 Register Field Descriptions
9.6.1.1.6
ASI_CFG1 Register (page = 0x00, address = 0x08) [reset = 0h]
Table 56.
ASI_CFG1 Register Field Descriptions
9.6.1.1.7
ASI_CFG2 Register (page = 0x00, address = 0x09) [reset = 0h]
Table 57.
ASI_CFG2 Register Field Descriptions
9.6.1.1.8
ASI_CH1 Register (page = 0x00, address = 0x0B) [reset = 0h]
Table 58.
ASI_CH1 Register Field Descriptions
9.6.1.1.9
ASI_CH2 Register (page = 0x00, address = 0x0C) [reset = 1h]
Table 59.
ASI_CH2 Register Field Descriptions
9.6.1.1.10
ASI_CH3 Register (page = 0x00, address = 0x0D) [reset = 2h]
Table 60.
ASI_CH3 Register Field Descriptions
9.6.1.1.11
ASI_CH4 Register (page = 0x00, address = 0x0E) [reset = 3h]
Table 61.
ASI_CH4 Register Field Descriptions
9.6.1.1.12
ASI_CH5 Register (page = 0x00, address = 0x0F) [reset = 4h]
Table 62.
ASI_CH5 Register Field Descriptions
9.6.1.1.13
ASI_CH6 Register (page = 0x00, address = 0x10) [reset = 5h]
Table 63.
ASI_CH6 Register Field Descriptions
9.6.1.1.14
ASI_CH7 Register (page = 0x00, address = 0x11) [reset = 6h]
Table 64.
ASI_CH7 Register Field Descriptions
9.6.1.1.15
ASI_CH8 Register (page = 0x00, address = 0x12) [reset = 7h]
Table 65.
ASI_CH8 Register Field Descriptions
9.6.1.1.16
MST_CFG0 Register (page = 0x00, address = 0x13) [reset = 2h]
Table 66.
MST_CFG0 Register Field Descriptions
9.6.1.1.17
MST_CFG1 Register (page = 0x00, address = 0x14) [reset = 48h]
Table 67.
MST_CFG1 Register Field Descriptions
9.6.1.1.18
ASI_STS Register (page = 0x00, address = 0x15) [reset = FFh]
Table 68.
ASI_STS Register Field Descriptions
9.6.1.1.19
CLK_SRC Register (page = 0x00, address = 0x16) [reset = 10h]
Table 69.
CLK_SRC Register Field Descriptions
9.6.1.1.20
PDMCLK_CFG Register (page = 0x00, address = 0x1F) [reset = 40h]
Table 70.
PDMCLK_CFG Register Field Descriptions
9.6.1.1.21
PDMIN_CFG Register (page = 0x00, address = 0x20) [reset = 0h]
Table 71.
PDMIN_CFG Register Field Descriptions
9.6.1.1.22
GPIO_CFG0 Register (page = 0x00, address = 0x21) [reset = 22h]
Table 72.
GPIO_CFG0 Register Field Descriptions
9.6.1.1.23
GPO_CFG0 Register (page = 0x00, address = 0x22) [reset = 0h]
Table 73.
GPO_CFG0 Register Field Descriptions
9.6.1.1.24
GPO_CFG1 Register (page = 0x00, address = 0x23) [reset = 0h]
Table 74.
GPO_CFG1 Register Field Descriptions
9.6.1.1.25
GPO_CFG2 Register (page = 0x00, address = 0x24) [reset = 0h]
Table 75.
GPO_CFG2 Register Field Descriptions
9.6.1.1.26
GPO_CFG3 Register (page = 0x00, address = 0x25) [reset = 0h]
Table 76.
GPO_CFG3 Register Field Descriptions
9.6.1.1.27
GPO_VAL Register (page = 0x00, address = 0x29) [reset = 0h]
Table 77.
GPO_VAL Register Field Descriptions
9.6.1.1.28
GPIO_MON Register (page = 0x00, address = 0x2A) [reset = 0h]
Table 78.
GPIO_MON Register Field Descriptions
9.6.1.1.29
GPI_CFG0 Register (page = 0x00, address = 0x2B) [reset = 0h]
Table 79.
GPI_CFG0 Register Field Descriptions
9.6.1.1.30
GPI_CFG1 Register (page = 0x00, address = 0x2C) [reset = 0h]
Table 80.
GPI_CFG1 Register Field Descriptions
9.6.1.1.31
GPI_MON Register (page = 0x00, address = 0x2F) [reset = 0h]
Table 81.
GPI_MON Register Field Descriptions
9.6.1.1.32
INT_CFG Register (page = 0x00, address = 0x32) [reset = 0h]
Table 82.
INT_CFG Register Field Descriptions
9.6.1.1.33
INT_MASK0 Register (page = 0x00, address = 0x33) [reset = FFh]
Table 83.
INT_MASK0 Register Field Descriptions
9.6.1.1.34
INT_LTCH0 Register (page = 0x00, address = 0x36) [reset = 0h]
Table 84.
INT_LTCH0 Register Field Descriptions
9.6.1.1.35
BIAS_CFG Register (page = 0x00, address = 0x3B) [reset = 0h]
Table 85.
BIAS_CFG Register Field Descriptions
9.6.1.1.36
CH1_CFG0 Register (page = 0x00, address = 0x3C) [reset = 0h]
Table 86.
CH1_CFG0 Register Field Descriptions
9.6.1.1.37
CH1_CFG1 Register (page = 0x00, address = 0x3D) [reset = 0h]
Table 87.
CH1_CFG1 Register Field Descriptions
9.6.1.1.38
CH1_CFG2 Register (page = 0x00, address = 0x3E) [reset = C9h]
Table 88.
CH1_CFG2 Register Field Descriptions
9.6.1.1.39
CH1_CFG3 Register (page = 0x00, address = 0x3F) [reset = 80h]
Table 89.
CH1_CFG3 Register Field Descriptions
9.6.1.1.40
CH1_CFG4 Register (page = 0x00, address = 0x40) [reset = 0h]
Table 90.
CH1_CFG4 Register Field Descriptions
9.6.1.1.41
CH2_CFG0 Register (page = 0x00, address = 0x41) [reset = 0h]
Table 91.
CH2_CFG0 Register Field Descriptions
9.6.1.1.42
CH2_CFG1 Register (page = 0x00, address = 0x42) [reset = 0h]
Table 92.
CH2_CFG1 Register Field Descriptions
9.6.1.1.43
CH2_CFG2 Register (page = 0x00, address = 0x43) [reset = C9h]
Table 93.
CH2_CFG2 Register Field Descriptions
9.6.1.1.44
CH2_CFG3 Register (page = 0x00, address = 0x44) [reset = 80h]
Table 94.
CH2_CFG3 Register Field Descriptions
9.6.1.1.45
CH2_CFG4 Register (page = 0x00, address = 0x45) [reset = 0h]
Table 95.
CH2_CFG4 Register Field Descriptions
9.6.1.1.46
CH3_CFG0 Register (page = 0x00, address = 0x46) [reset = 0h]
Table 96.
CH3_CFG0 Register Field Descriptions
9.6.1.1.47
CH3_CFG1 Register (page = 0x00, address = 0x47) [reset = 0h]
Table 97.
CH3_CFG1 Register Field Descriptions
9.6.1.1.48
CH3_CFG2 Register (page = 0x00, address = 0x48) [reset = C9h]
Table 98.
CH3_CFG2 Register Field Descriptions
9.6.1.1.49
CH3_CFG3 Register (page = 0x00, address = 0x49) [reset = 80h]
Table 99.
CH3_CFG3 Register Field Descriptions
9.6.1.1.50
CH3_CFG4 Register (page = 0x00, address = 0x4A) [reset = 0h]
Table 100.
CH3_CFG4 Register Field Descriptions
9.6.1.1.51
CH4_CFG0 Register (page = 0x00, address = 0x4B) [reset = 0h]
Table 101.
CH4_CFG0 Register Field Descriptions
9.6.1.1.52
CH4_CFG1 Register (page = 0x00, address = 0x4C) [reset = 0h]
Table 102.
CH4_CFG1 Register Field Descriptions
9.6.1.1.53
CH4_CFG2 Register (page = 0x00, address = 0x4D) [reset = C9h]
Table 103.
CH4_CFG2 Register Field Descriptions
9.6.1.1.54
CH4_CFG3 Register (page = 0x00, address = 0x4E) [reset = 80h]
Table 104.
CH4_CFG3 Register Field Descriptions
9.6.1.1.55
CH4_CFG4 Register (page = 0x00, address = 0x4F) [reset = 0h]
Table 105.
CH4_CFG4 Register Field Descriptions
9.6.1.1.56
CH5_CFG2 Register (page = 0x00, address = 0x52) [reset = C9h]
Table 106.
CH5_CFG2 Register Field Descriptions
9.6.1.1.57
CH5_CFG3 Register (page = 0x00, address = 0x53) [reset = 80h]
Table 107.
CH5_CFG3 Register Field Descriptions
9.6.1.1.58
CH5_CFG4 Register (page = 0x00, address = 0x54) [reset = 0h]
Table 108.
CH5_CFG4 Register Field Descriptions
9.6.1.1.59
CH6_CFG2 Register (page = 0x00, address = 0x57) [reset = C9h]
Table 109.
CH6_CFG2 Register Field Descriptions
9.6.1.1.60
CH6_CFG3 Register (page = 0x00, address = 0x58) [reset = 80h]
Table 110.
CH6_CFG3 Register Field Descriptions
9.6.1.1.61
CH6_CFG4 Register (page = 0x00, address = 0x59) [reset = 0h]
Table 111.
CH6_CFG4 Register Field Descriptions
9.6.1.1.62
CH7_CFG2 Register (page = 0x00, address = 0x5C) [reset = C9h]
Table 112.
CH7_CFG2 Register Field Descriptions
9.6.1.1.63
CH7_CFG3 Register (page = 0x00, address = 0x5D) [reset = 80h]
Table 113.
CH7_CFG3 Register Field Descriptions
9.6.1.1.64
CH7_CFG4 Register (page = 0x00, address = 0x5E) [reset = 0h]
Table 114.
CH7_CFG4 Register Field Descriptions
9.6.1.1.65
CH8_CFG2 Register (page = 0x00, address = 0x61) [reset = C9h]
Table 115.
CH8_CFG2 Register Field Descriptions
9.6.1.1.66
CH8_CFG3 Register (page = 0x00, address = 0x62) [reset = 80h]
Table 116.
CH8_CFG3 Register Field Descriptions
9.6.1.1.67
CH8_CFG4 Register (page = 0x00, address = 0x63) [reset = 0h]
Table 117.
CH8_CFG4 Register Field Descriptions
9.6.1.1.68
DSP_CFG0 Register (page = 0x00, address = 0x6B) [reset = 1h]
Table 118.
DSP_CFG0 Register Field Descriptions
9.6.1.1.69
DSP_CFG1 Register (page = 0x00, address = 0x6C) [reset = 40h]
Table 119.
DSP_CFG1 Register Field Descriptions
9.6.1.1.70
AGC_CFG0 Register (page = 0x00, address = 0x70) [reset = E7h]
Table 120.
AGC_CFG0 Register Field Descriptions
9.6.1.1.71
IN_CH_EN Register (page = 0x00, address = 0x73) [reset = F0h]
Table 121.
IN_CH_EN Register Field Descriptions
9.6.1.1.72
ASI_OUT_CH_EN Register (page = 0x00, address = 0x74) [reset = 0h]
Table 122.
ASI_OUT_CH_EN Register Field Descriptions
9.6.1.1.73
PWR_CFG Register (page = 0x00, address = 0x75) [reset = 0h]
Table 123.
PWR_CFG Register Field Descriptions
9.6.1.1.74
DEV_STS0 Register (page = 0x00, address = 0x76) [reset = 0h]
Table 124.
DEV_STS0 Register Field Descriptions
9.6.1.1.75
DEV_STS1 Register (page = 0x00, address = 0x77) [reset = 80h]
Table 125.
DEV_STS1 Register Field Descriptions
9.6.1.1.76
I2C_CKSUM Register (page = 0x00, address = 0x7E) [reset = 0h]
Table 126.
I2C_CKSUM Register Field Descriptions
9.6.2
Programmable Coefficient Registers
9.6.2.1
Programmable Coefficient Registers: Page = 0x02
9.6.2.2
Programmable Coefficient Registers: Page = 0x03
9.6.2.3
Programmable Coefficient Registers: Page = 0x04
10
Application and Implementation
10.1
Application Information
10.2
Typical Applications
10.2.1
Four-Channel Analog Microphone Recording
10.2.1.1
Design Requirements
10.2.1.2
Detailed Design Procedure
10.2.1.2.1
Example Device Register Configuration Script for EVM Setup
10.2.1.3
Application Curves
10.2.2
Eight-Channel Digital PDM Microphone Recording
10.2.2.1
Design Requirements
10.2.2.2
Detailed Design Procedure
10.2.2.2.1
Example Device Register Configuration Script for EVM Setup
10.3
What to Do and What Not to Do
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
デバイスおよびドキュメントのサポート
13.1
ドキュメントのサポート
13.1.1
関連資料
13.2
ドキュメントの更新通知を受け取る方法
13.3
コミュニティ・リソース
13.4
商標
13.5
静電気放電に関する注意事項
13.6
Glossary
14
メカニカル、パッケージ、および注文情報
10.2
Typical Applications