9.6.12 SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0]
SEQUENCE_CFG is shown in Figure 30 and described in Table 26.
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Figure 30. SEQUENCE_CFG Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
SEQ_START |
RESERVED |
SEQ_MODE[1:0] |
R-0b |
R/W-0b |
R-0b |
R/W-0b |
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Table 26. SEQUENCE_CFG Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-5 |
RESERVED |
R |
0b |
Reserved. Reads return 0. |
4 |
SEQ_START |
R/W |
0b |
Control for start of channel sequence when using auto sequence mode (SEQ_MODE = 01b).
0b = Stop channel sequencing.
1b = Start channel sequencing in ascending order for channels enabled in AUTO_SEQ_CH_SEL register.
|
3-2 |
RESERVED |
R |
0b |
Reserved. Reads return 0. |
1-0 |
SEQ_MODE[1:0] |
R/W |
0b |
Selects the mode of scanning of analog input channels.
0b = Manual sequence mode; channel selected by MANUAL_CHID field.
1b = Auto sequence mode; channel selected by internal channel sequencer.
10b = Reserved.
11b = Reserved.
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