JAJSHK9C June 2019 – September 2024 ADS7038
PRODUCTION DATA
The ADS7028 features a cyclic redundancy check (CRC) module for checking the integrity of the data bits exchanged over the SPI interface. The CRC module is bidirectional, which appends an 8-bit CRC to every byte read from the device and also evaluates the CRC of every incoming byte over the SPI interface. The CRC module uses the CRC-8-CCITT polynomial (x8 + x2 + x + 1) for CRC computation.
To enable the CRC module, set the CRC_EN bit in the GENERAL_CFG register. Table 7-4 shows the different ways that a CRC error that occurs when configuring the ADS7028 can be detected.
CRC ERROR NOTIFICATION | CONFIGURATION | DESCRIPTION |
---|---|---|
ALERT | ALERT_CRCIN = 1b | ALERT (internal signal) is asserted if a CRC error is detected |
Status flags | APPEND_STATUS = 10b | 4-bit status flags are appended to the ADC data. See the Output Data Format section for details. |
Register read | — | Read the CRCERR_IN bit to check if a CRC error was detected. |
When the ADS7028 detects a CRC error on the SPI interface, the erroneous data are ignored and the CRCERR_IN bit is set. Additional notifications can be enabled as described in Table 7-4. Further register writes are disabled until the CRCERR_IN bit is cleared by writing 1b to this bit. When using autonomous conversion mode, further conversions can be disabled on a CRC error on the SPI interface by setting CONV_ON_ERR = 1b.