JAJSHZ5D September   2019  – November 2023 UCC21750-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Safety-Related Certifications
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay
      1. 7.1.1 Regular Turn-OFF
    2. 7.2 Input Deglitch Filter
    3. 7.3 Active Miller Clamp
      1. 7.3.1 Internal On-Chip Active Miller Clamp
    4. 7.4 Undervoltage Lockout (UVLO)
      1. 7.4.1 VCC UVLO
      2. 7.4.2 VDD UVLO
    5. 7.5 Desaturation (DESAT) Protection
      1. 7.5.1 DESAT Protection with Soft Turn-OFF
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power Supply
      2. 8.3.2  Driver Stage
      3. 8.3.3  VCC and VDD Undervoltage Lockout (UVLO)
      4. 8.3.4  Active Pulldown
      5. 8.3.5  Short Circuit Clamping
      6. 8.3.6  Internal Active Miller Clamp
      7. 8.3.7  Desaturation (DESAT) Protection
      8. 8.3.8  Soft Turn-Off
      9. 8.3.9  Fault (FLT, Reset, and Enable (RST/EN)
      10. 8.3.10 Isolated Analog to PWM Signal Function
    4. 8.4 Device Functional Modes
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Filters for IN+, IN–, and RST/EN
        2. 9.2.2.2 PWM Interlock of IN+ and IN–
        3. 9.2.2.3 FLT, RDY, and RST/EN Pin Circuitry
        4. 9.2.2.4 RST/EN Pin Control
        5. 9.2.2.5 Turn-On and Turn-Off Gate Resistors
        6. 9.2.2.6 Overcurrent and Short Circuit Protection
        7. 9.2.2.7 Isolated Analog Signal Sensing
          1. 9.2.2.7.1 Isolated Temperature Sensing
          2. 9.2.2.7.2 Isolated DC Bus Voltage Sensing
        8. 9.2.2.8 Higher Output Current Using an External Current Buffer
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Mechanical, Packaging, and Orderable Information

6.8 Electrical Characteristics

VCC = 3.3 V or 5.0 V, 1-µF capacitor from VCC to GND, VDD – COM = 20 V, 18 V or 15 V, COM – VEE = 0 V, 5 V, 8 V or 15 V, CL = 100 pF, –40°C < TJ < 150°C (unless otherwise noted)(1)(2).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC UVLO THRESHOLD AND DELAY
VVCC_ON VCC–GND 2.55 2.7 2.85 V
VVCC_OFF 2.35 2.5 2.65
VVCC_HYS 0.2
tVCCFIL VCC UVLO Deglitch time 10 µs
tVCC+ to OUT VCC UVLO on delay to output high IN+ = VCC, IN– = GND 28 37.8 50
tVCC– to OUT VCC UVLO off delay to output low 5 10 15
tVCC+ to RDY VCC UVLO on delay to RDY high RST/EN = VCC 30 37.8 50
tVCC– to RDY VCC UVLO off delay to RDY low 5 10 15
VDD UVLO THRESHOLD AND DELAY
VVDD_ON VDD–COM 10.5 12.0 12.8 V
VVDD_OFF 9.9 10.7 11.8
VVDD_HYS 0.8
tVDDFIL VDD UVLO Deglitch time 5 µs
tVDD+ to OUT VDD UVLO on delay to output high IN+ = VCC, IN– = GND 2 5 8
tVDD– to OUT VDD UVLO off delay to output low 5 10
tVDD+ to RDY VDD UVLO on delay to RDY high RST/EN = FLT=High 10 15
tVDD– to RDY VDD UVLO off delay to RDY low 10 15
VCC, VDD QUIESCENT CURRENT
IVCCQ VCC quiescent current OUT(H) = High, fS = 0Hz, AIN = 2 V 2.5 3 4 mA
OUT(L) = Low, fS = 0Hz, AIN = 2 V 1.45 2 2.75
IVDDQ VDD quiescent current OUT(H) = High, fS = 0Hz, AIN = 2 V 3.6 4 5.9 mA
OUT(L) = Low, fS = 0Hz, AIN = 2 V 3.1 3.7 5.3
LOGIC INPUTS — IN+, IN– and RST/EN
VINH Input high threshold VCC = 3.3 V 1.85 2.31 V
VINL Input low threshold VCC = 3.3 V 0.99 1.52 V
VINHYS Input threshold hysteresis VCC = 3.3 V 0.33 V
IIH Input high level input leakage current VIN = VCC 90 µA
IIL Input low level input leakage VIN = GND –90 µA
RIND Input pins pull down resistance see Detailed Description for more information 55 kΩ
RINU Input pins pull up resistance see Detailed Description for more information 55
TINFIL IN+, IN– and RST/EN deglitch (ON and OFF) filter time fS = 50 kHz 28 40 60 ns
TRSTFIL Deglitch filter time to reset /FLT 400 650 800 ns
GATE DRIVER STAGE
IOUT, IOUTH Peak source current CL = 0.18 µF, fS = 1 kHz 10 A
IOUT, IOUTL Peak sink current 10 A
ROUTH(3) Output pull-up resistance IOUT = –0.1 A 2.5 Ω
ROUTL Output pull-down resistance IOUT = 0.1 A 0.3 Ω
VOUTH High level output voltage IOUT = –0.2 A, VDD = 18 V 17.5 V
VOUTL Low level output voltage IOUT = 0.2 A 60 mV
ACTIVE PULLDOWN
VOUTPD Output active pull down on OUT, OUTL IOUTL or IOUT = 0.1 × IOUT(L)(tpy), VDD=OPEN, VEE=COM 1.5 2 2.5 V
INTERNAL ACTIVE MILLER CLAMP
VCLMPTH Miller clamp threshold voltage Reference to VEE 1.5 2.0 2.5 V
VCLMPI Output low clamp voltage ICLMPI = 1 A VEE + 0.5 V
ICLMPI Output low clamp current VCLMPI = 0 V, VEE = –2.5 V 4 A
RCLMPI Miller clamp pull down resistance ICLMPI = 0.2 A 0.6 Ω
tDCLMPI Miller clamp ON delay time CL = 1.8 nF 15 50 ns
SHORT CIRCUIT CLAMPING
VCLP-OUT(H) VOUT–VDD, VOUTH–VDD OUT = Low, IOUT(H) = 500 mA, tCLP =1 0 us 0.9 V
VCLP-OUT(L) VOUT–VDD, VOUTL–VDD OUT = High, IOUT(L) = 500 mA, tCLP = 10 us 1.8 V
VCLP-CLMPI VCLMPI–VDD OUT = High, ICLMPI = 20 mA, tCLP = 10 us 1.0 V
DESAT PROTECTION
ICHG Blanking capacitor charge current VDESAT = 2.0 V 430 500 570 µA
IDCHG Blanking capacitor discharge current VDESAT = 6.0 V 10 15 mA
VDESAT Detection Threshold 8.5 9.15 9.8 V
tDESATLEB Leading edge blank time 200 ns
tDESATFIL DESAT deglitch filter 50 140 230 ns
tDESATOFF DESAT propagation delay to OUT(L) 90% 150 200 300 ns
tDESATFLT DESAT to FLT low delay 400 580 750 ns
INTERNAL SOFT TURN-OFF
ISTO Soft turn-off current on fault conditions VDD-VEE=20V, VOUTL-COM=8V 250 400 570 mA
ISOLATED TEMPERATURE SENSE AND MONITOR (AIN–APWM)
VAIN Analog sensing voltage range 0.6 4.5 V
IAIN Internal current source
 VAIN = 2.5 V, -40°C < TJ< 150°C
 196 200 209 µA
fAPWM APWM output frequency VAIN = 2.5 V 380 400 420 kHz
BWAIN AIN–APWM bandwidth 10 kHz
DAPWM APWM Dutycycle VAIN = 0.6 V 86.5 88 89.5 %
VAIN = 2.5 V 48.5 50 51.5
VAIN = 4.5 V 7.5 10 11.5
FLT AND RDY REPORTING
tRDYHLD VDD UVLO RDY low minimum holding time 0.55 1 ms
tFLTMUTE Output mute time on fault Reset fault through RST/EN 0.55 1 ms
RODON Open drain output on resistance IODON = 5 mA 30 Ω
VODL Open drain low output voltage IODON = 5 mA 0.3 V
COMMON MODE TRANSIENT IMMUNITY
CMTI Common-mode transient immunity 150 V/ns
(1) Current are positive into and negative out of the specified terminal.
(2) All voltages are referenced to COM unless otherwise notified.
(3) For internal PMOS only. Refer to Section 8.3.2 for effective pull-up resistance.