JAJSI70C
May 2008 – November 2019
DAC9881
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
ブロック図
4
改訂履歴
5
概要(続き)
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics: AVDD = 5 V
7.6
Electrical Characteristics: AVDD = 2.7 V
7.7
Timing Requirements—Standalone Operation Without SDO
7.8
Timing Requirements—Standalone Operation With SDO and Daisy-Chain Mode
7.9
Typical Characteristics: AVDD = 5 V
7.10
Typical Characteristics: AVDD = 2.7 V
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Analog Output
8.3.2
Reference Inputs
8.3.3
Output Range
8.3.4
Input Data Format
8.3.5
Hardware Reset
8.3.6
Power-On Reset
8.3.6.1
Program Reset Value
8.3.7
Power Down
8.3.8
Double-Buffered Interface
8.3.8.1
Load DAC Pin (LDAC)
8.3.8.1.1
Synchronous Mode
8.3.8.1.2
Asynchronous Mode
8.3.9
1.8-V to 5-V Logic Interface
8.3.10
Power-Supply Sequence
8.4
Device Functional Modes
8.4.1
Serial Interface
8.4.1.1
Input Shift Register
8.4.1.1.1
Stand-Alone Mode
8.4.1.1.2
Daisy-Chain Mode
9
Application and Implementation
9.1
Application Information
9.1.1
Bipolar Operation Using the DAC9881
9.2
Typical Application
9.2.1
DAC9881 Sample-and-Hold Circuit
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curves
9.3
System Example
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
デバイスおよびドキュメントのサポート
12.1
ドキュメントのサポート
12.1.1
関連資料
12.2
ドキュメントの更新通知を受け取る方法
12.3
サポート・リソース
12.4
商標
12.5
静電気放電に関する注意事項
12.6
Glossary
13
メカニカル、パッケージ、および注文情報
9.2.1
DAC9881 Sample-and-Hold Circuit
Figure 71.
DAC9881 Sample-and-Hold Circuit