JAJSIA4C December   2019  – June 2022 TLIN2021-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Thermal Information
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Power Supply Characteristics
    6. 7.6 Electrical Characteristics
    7. 7.7 AC Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  LIN
        1. 9.3.1.1 LIN Transmitter Characteristics
        2. 9.3.1.2 LIN Receiver Characteristics
          1. 9.3.1.2.1 Termination
      2. 9.3.2  TXD
      3. 9.3.3  RXD
      4. 9.3.4  VSUP
      5. 9.3.5  GND
      6. 9.3.6  EN
      7. 9.3.7  WAKE
      8. 9.3.8  INH
      9. 9.3.9  Local Faults
      10. 9.3.10 TXD Dominant Time-Out (DTO)
      11. 9.3.11 Bus Stuck Dominant System Fault: False Wake-Up Lockout
      12. 9.3.12 Thermal Shutdown
      13. 9.3.13 Under Voltage on VSUP
      14. 9.3.14 Unpowered Device
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Sleep Mode
      3. 9.4.3 Standby Mode
      4. 9.4.4 Wake-Up Events
        1. 9.4.4.1 Local Wake-Up (LWU) via WAKE Input Terminal
        2. 9.4.4.2 Wake-Up Request (RXD)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 Normal Mode Application Note
        2. 10.2.2.2 TXD Dominant State Time-Out Application Note
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4.     Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

9.3.10 TXD Dominant Time-Out (DTO)

While the LIN driver is in active mode a TXD DTO circuit prevents the local node from blocking network communication in event of a hardware or software failure where TXD is held dominant longer than the time-out period tTXD_DTO. The TXD DTO circuit is triggered by a falling edge on TXD. If no rising edge is seen before the time-out constant of the circuit, tTXD_DTO, expires the LIN driver is disabled releasing the bus line to the recessive level. This keeps the bus free for communication between other nodes on the network. The LIN driver is re-activated on the next dominant to recessive transition on the TXD terminal, thus clearing the dominant time-out. During this fault, the transceiver remains in normal mode, the integrated LIN bus pull-up termination remains on, and the LIN receiver and RXD terminal remain active reflecting the LIN bus data.

The TXD pin has an internal pull-down to ensure the device fails to a known state if TXD is disconnected. If EN pin is high at power-up, the TLIN2021-Q1 enters normal mode. With the internal TXD connected low, the DTO timer starts. To avoid a tTXD_DTO fault, a recessive signal should be put onto the TXD pin before the tTXD_DTO timer expires, or the device should be into sleep mode by connecting EN pin low.