JAJSIA4C December   2019  – June 2022 TLIN2021-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Thermal Information
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Power Supply Characteristics
    6. 7.6 Electrical Characteristics
    7. 7.7 AC Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  LIN
        1. 9.3.1.1 LIN Transmitter Characteristics
        2. 9.3.1.2 LIN Receiver Characteristics
          1. 9.3.1.2.1 Termination
      2. 9.3.2  TXD
      3. 9.3.3  RXD
      4. 9.3.4  VSUP
      5. 9.3.5  GND
      6. 9.3.6  EN
      7. 9.3.7  WAKE
      8. 9.3.8  INH
      9. 9.3.9  Local Faults
      10. 9.3.10 TXD Dominant Time-Out (DTO)
      11. 9.3.11 Bus Stuck Dominant System Fault: False Wake-Up Lockout
      12. 9.3.12 Thermal Shutdown
      13. 9.3.13 Under Voltage on VSUP
      14. 9.3.14 Unpowered Device
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Sleep Mode
      3. 9.4.3 Standby Mode
      4. 9.4.4 Wake-Up Events
        1. 9.4.4.1 Local Wake-Up (LWU) via WAKE Input Terminal
        2. 9.4.4.2 Wake-Up Request (RXD)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 Normal Mode Application Note
        2. 10.2.2.2 TXD Dominant State Time-Out Application Note
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4.     Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.6 Electrical Characteristics

parameters valid across -40℃ ≤ TJ ≤ 150℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RXD Output Terminal
VOL Low-level voltage Based upon external pull-up to VCC(3) 0.6 V
IOL Low-level output current, open drain LIN = 0 V, RXD = 0.4 V 1.5 mA
ILKG Leakage current, high-level LIN = VSUP, RXD = VCC –5 5 µA
TXD Input Terminal
VIL Low-level input voltage 0.8 V
VIH High-level input voltage 2 V
ILKG Low-level input leakage current TXD = 0 V –5 5 µA
ITXD(WAKE) Local wake-up source recognition TXD(4) Standby mode after a local wake-up event
VLIN = VSUP, WAKE = 0 V or VSUP, TXD = 1 V		 1.3 8 mA
RTXD Internal pull-down resistor value 125 350 800 kΩ
EN Input Terminal
VIL Low-level input voltage –0.3 0.8 V
VIH High-level input voltage 2 5.25 V
VHYS Hysteresis voltage By design and characterization 30 500 mV
IIL Low-level input current EN = 0 V –5 5 µA
REN Internal pull-down resistor 125 350 800 kΩ
LIN Terminal (Referenced to VSUP)
VOH LIN recessive high-level output voltage TXD = VCC, IO = 0 mA, VSUP = 7 V to 45 V 0.85 VSUP
VOH LIN recessive high-level output voltage TXD = VCC, IO = 0 mA, 4.5 V ≤ VSUP ≤ 7 V 3 V
VOL LIN dominant low-level output voltage TXD = 0 V, VSUP = 7 V to 45 V 0.2 VSUP
VOL LIN dominant low-level output voltage TXD = 0 V, 4.5 V ≤ VSUP ≤ 7 V 1.2 V
VSUP_NON_OP VSUP where impact of recessive LIN bus < 5%
ISO 17987 Param 54/56		 TXD & RXD open LIN = 4.5 V to 60 V –0.3 60 V
IBUS(LIM) Limiting current
ISO 17987 Param 57		 TXD = 0 V, VLIN = 36 V, RMEAS = 480 Ω, VSUP = 36 V, VBUSdom < 10.224 V
See Figure 8-6		 75 120 300 mA
IBUS_PAS_dom Receiver leakage current, dominant
ISO 17987 Param 58		 Driver off/recessive, LIN = 0 V, VSUP = 24 V
See Figure 8-7		 –1 mA
IBUS_PAS_rec1 Receiver leakage current, recessive
ISO 17987 Param 59		 Driver off/recessive, LIN ≥ VSUP, 4.5 V ≤ VSUP ≤ 45 V
See Figure 8-8		 20 µA
IBUS_PAS_rec2 Receiver leakage current, recessive
ISO 17987 Param 59		 Driver off/recessive, LIN = VSUP
See Figure 8-8		 –5 5 µA
IBUS_NO_GND Leakage current, loss of ground
ISO 17987 Param 60		 GND = VSUP = 27 V, 0 V ≤ VLIN ≤ 36 V
See Figure 8-9		 –1.5 1.5 mA
IBUS_NO_BAT Leakage current, loss of supply
ISO 17987 Param 61		 VSUP = GND, 0 V ≤ VLIN ≤ 36 V
See Figure 8-9		 5 µA
VBUSdom Low-level input voltage
ISO 17987 Param 62		 LIN dominant (including LIN dominant for wake up)
See Figure 8-3 and Figure 8-4		 0.4 VSUP
VBUSrec High-level input voltage
ISO 17987 Param 63		 Lin recessive
See Figure 8-3 and Figure 8-4		 0.6 VSUP
VBUS_CNT Receiver center threshold
ISO 17987 Param 64		 VBUS_CNT = (VBUSrec + VBUSdom)/2
See Figure 8-3 and Figure 8-4		 0.475 0.5 0.525 VSUP
VHYS Hysteresis voltage
ISO 17987 Param 65		 VHYS = VBUSrec - VBUSdom
See Figure 8-3 and Figure 8-4		 0.175 VSUP
VSERIAL_DIODE Serial diode LIN termination pull-up path ISERIAL_DIODE = 10 µA 0.4 0.7 1.0 V
RResponder Pull-up resistor to VSUP Normal and standby modes 20 45 60 kΩ
IRSLEEP Pull-up current source to VSUP sleep mode VSUP = 27 V, LIN = GND –20 –1.5 µA
CLIN Capacitance of the LIN pin 25
pF
INH Output Terminal
ΔVH High level voltage drop INH with respect to VSUP IINH = - 0.5 mA 0.5 1 V
ILKG(INH) Leakage current sleep mode INH = 0 V –0.5 0.5 µA
WAKE Input Terminal
VIH High-level input voltage Standby and sleep mode VSUP – 1.8 V
VIL Low-level input voltage Standby and sleep mode VSUP – 3.85 V
IIH High-level input leakage current WAKE = VSUP - 1 V –25 –12.5 µA
IIL Ligh-level input leakage current WAKE = 1 V 15 25 µA
tWAKE WAKE hold time Wake up time from sleep mode 5 50 µs
Duty Cycle Characteristics(5)
D112V Duty Cycle 1
ISO 17987 Param 27(1)		 THREC(MAX) = 0.744 x VSUP,
THDOM(MAX) = 0.581 x VSUP,
VSUP = 7 V to 18 V, tBIT = 50 µs (20 kbps),
D1 = tBUS_rec(min)/(2 x tBIT)
See Figure 8-10 and Figure 8-11		 0.396
D112V Duty Cycle 1 THREC(MAX) = 0.625 x VSUP,
THDOM(MAX) = 0.581 x VSUP,
VSUP = 4.5 V to 7 V, tBIT = 50 µs (20 kbps),
D1 = tBUS_rec(min)/(2 x tBIT)
See Figure 8-10 and Figure 8-11		 0.396
D212V Duty Cycle 2
ISO 17987 Param 28		 THREC(MIN) = 0.422 x VSUP,
THDOM(MIN) = 0.284 x VSUP,
VSUP = 4.5 V to 18 V, tBIT = 50 µs (20 kbps),
D2 = tBUS_rec(MAX)/(2 x tBIT)
See Figure 8-10 and Figure 8-11		 0.581
D312V Duty Cycle 3
ISO 17987 Param 29(2)		 THREC(MAX) = 0.778 x VSUP,
THDOM(MAX) = 0.616 x VSUP,
VSUP = 7 V to 18 V, tBIT = 96 µs (10.4 kbps),
D3 = tBUS_rec(min)/(2 x tBIT)
See Figure 8-10 and Figure 8-11		 0.417
D312V Duty Cycle 3 THREC(MAX) = 0.645 x VSUP, THDOM(MAX) = 0.616 x VSUP, VSUP = 4.5 V to 7 V, tBIT = 96 µs (10.4 kbps),
D3 = tBUS_rec(min)/(2 x tBIT)
See Figure 8-10 and Figure 8-11		 0.417
D412V Duty Cycle 4
ISO 17987 Param 30		 THREC(MIN) = 0.389 x VSUP,
THDOM(MIN) = 0.251 x VSUP,
VSUP = 7 V to 18 V, tBIT = 96 µs (10.4 kbps),
D4 = tBUS_rec(MAX)/(2 x tBIT)
See Figure 8-10 and Figure 8-11		 0.59
D412V Duty Cycle 4 THREC(MIN) = 0.422 x VSUP,
THDOM(MIN) = 0.284 x VSUP,
VSUP = 4.5 V to 7 V, tBIT = 96 µs (10.4 kbps),
D4 = tBUS_rec(MAX)/(2 x tBIT)
See Figure 8-10 and Figure 8-11		 0.59
D124V Duty Cycle 1
ISO 17987 Param 72		 THREC(MAX) = 0.710 x VSUP,
THDOM(MAX) = 0.554 x VSUP,
VSUP = 15 V to 36 V, tBIT = 50 µs, D1 = tBUS_rec(MIN)/(2 x tBIT)
See Figure 8-12 and Figure 8-13		 0.330
D224V Duty Cycle 2
ISO 17987 Param 73		 THREC(MIN) = 0.446 x VSUP,
THDOM(MIN) = 0.302 x VSUP,
VSUP = 15.6 V to 36 V, tBIT = 50 µs, D2 = tBUS_rec(MAX)/(2 x tBIT)
See Figure 8-12 and Figure 8-13		 0.642
D324V Duty Cycle 3
ISO 17987 Param 74		 THREC(MAX) = 0.744 x VSUP,
THDOM(MAX) = 0.581 x VSUP,
VSUP = 7 V to 36 V, tBIT = 96 µs, D3 = tBUS_rec(min)/(2 x tBIT)
See Figure 8-12 and Figure 8-13		 0.386
D324V Duty Cycle 3 THREC(MAX) = 0.645 x VSUP,
THDOM(MAX) = 0.581 x VSUP,
VSUP = 4.5 V to 7 V, tBIT = 96 µs, D3 = tBUS_rec(min)/(2 x tBIT)
See Figure 8-12 and Figure 8-13		 0.386
D424V Duty Cycle 4
ISO 17987 Param 75		 THREC(MIN) = 0.422 x VSUP,
THDOM(MIN) = 0.284 x VSUP,
VSUP = 4.5 V to 36 V, tBIT = 96 µs, D4 = tBUS_rec(MAX)/(2 x tBIT)
See Figure 8-12 and Figure 8-13		 0.591
(1) Duty cycle LIN driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF; 1 kΩ / Load2 = 6.8 nF; 660 Ω / Load3 = 10 nF; 500 Ω.
(2) Duty cycles 3 and 4 are defined for 10.4-kbps operation. The TLIN2029 meets these lower data rate requirements while it is also capable of the higher speed 20-kbps operation as specified by duty cycles 1 and 2. SAE J2602 derives propagation delay equations from the LIN 2.0 duty cycle definitions, for details see the SAE J2602 specification.
(3) RXD uses open drain output structure therefore VOL level is based upon microcontroller supply voltage.
(4) Open drain-drive