JAJSIK5D February   2020  – February 2024 AWR2243

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 機能ブロック図
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Power-On Hours (POH)
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Power Supply Specifications
    6. 7.6 Power Consumption Summary
    7. 7.7 RF Specification
    8. 7.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 7.9 Timing and Switching Characteristics
      1. 7.9.1 Power Supply Sequencing and Reset Timing
      2. 7.9.2 Synchronized Frame Triggering
      3. 7.9.3 Input Clocks and Oscillators
        1. 7.9.3.1 Clock Specifications
      4. 7.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.9.4.1 Peripheral Description
          1. 7.9.4.1.1 SPI Timing Conditions
          2. 7.9.4.1.2 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. 7.9.4.1.3 SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 7.9.4.2 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 7.9.5 Inter-Integrated Circuit Interface (I2C)
        1. 7.9.5.1 I2C Timing Requirements
      6. 7.9.6 LVDS Interface Configuration
        1. 7.9.6.1 LVDS Interface Timings
      7. 7.9.7 General-Purpose Input/Output
        1. 7.9.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 7.9.8 Camera Serial Interface (CSI)
        1. 7.9.8.1 CSI Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Host Interface
    4. 8.4 Other Subsystems
      1. 8.4.1 ADC Data Format Over CSI2 Interface
      2. 8.4.2 ADC Channels (Service) for User Application
        1. 8.4.2.1 GPADC Parameters
  10. 9 Monitoring and Diagnostic Mechanisms
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short-, Medium-, and Long-Range Radar
    3. 10.3 Imaging Radar using Cascade Configuration
    4. 10.4 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Export Control Notice
    8. 11.8 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

8.3.1.2 Transmit Subsystem

The AWR2243 transmit subsystem consists of three parallel transmit chains, each with independent phase and amplitude control. All three transmitters can be used simultaneously or in time-multiplexed fashion. The device supports binary phase modulation for MIMO radar and interference mitigation. For AWR2243, additional phase shifters are associated with Tx channels, and these can programmed on a per chirp basis.

Each transmit chain can deliver a maximum of 13 dBm at the antenna port on the PCB. The transmit chains also support programmable backoff for system optimization.

Figure 8-2 describes the transmit subsystem.

AWR2243 Transmit Subsystem (Per Channel)Figure 8-2 Transmit Subsystem (Per Channel)