JAJSIK5D February   2020  – February 2024 AWR2243

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 機能ブロック図
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Power-On Hours (POH)
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Power Supply Specifications
    6. 7.6 Power Consumption Summary
    7. 7.7 RF Specification
    8. 7.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 7.9 Timing and Switching Characteristics
      1. 7.9.1 Power Supply Sequencing and Reset Timing
      2. 7.9.2 Synchronized Frame Triggering
      3. 7.9.3 Input Clocks and Oscillators
        1. 7.9.3.1 Clock Specifications
      4. 7.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.9.4.1 Peripheral Description
          1. 7.9.4.1.1 SPI Timing Conditions
          2. 7.9.4.1.2 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. 7.9.4.1.3 SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 7.9.4.2 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 7.9.5 Inter-Integrated Circuit Interface (I2C)
        1. 7.9.5.1 I2C Timing Requirements
      6. 7.9.6 LVDS Interface Configuration
        1. 7.9.6.1 LVDS Interface Timings
      7. 7.9.7 General-Purpose Input/Output
        1. 7.9.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 7.9.8 Camera Serial Interface (CSI)
        1. 7.9.8.1 CSI Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Host Interface
    4. 8.4 Other Subsystems
      1. 8.4.1 ADC Data Format Over CSI2 Interface
      2. 8.4.2 ADC Channels (Service) for User Application
        1. 8.4.2.1 GPADC Parameters
  10. 9 Monitoring and Diagnostic Mechanisms
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short-, Medium-, and Long-Range Radar
    3. 10.3 Imaging Radar using Cascade Configuration
    4. 10.4 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Export Control Notice
    8. 11.8 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MINNOMMAXUNIT
VDDIN1.2 V digital power supply1.141.21.32V
VIN_SRAM1.2 V power rail for internal SRAM1.141.21.32V
VNWA1.2 V power rail for SRAM array back bias1.141.21.32V
VIOINI/O supply (3.3 V or 1.8 V):
All CMOS I/Os would operate on this supply.		3.1353.33.465V
1.711.81.89
VIOIN_181.8 V supply for CMOS IO1.711.81.9V
VIN_18CLK1.8 V supply for clock module1.711.81.9V
VIOIN_18DIFF1.8 V supply for CSI2 port1.711.81.9V
VIN_13RF11.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2 could be shorted on the board1.231.31.36V
VIN_13RF2
VIN_13RF1
(1-V Internal LDO bypass mode)		0.9511.05V
VIN_13RF2
(1-V Internal LDO bypass mode)
VIN18BB1.8-V Analog baseband power supply1.711.81.9V
VIN_18VCO1.8V RF VCO supply1.711.81.9V
VIHVoltage Input High (1.8 V mode)1.17V
Voltage Input High (3.3 V mode)2.25
VILVoltage Input Low (1.8 V mode)0.3*VIOINV
Voltage Input Low (3.3 V mode)0.62
VOHHigh-level output threshold (IOH = 6 mA)VIOIN – 450mV
VOLLow-level output threshold (IOL = 6 mA)450mV
NRESET SOP[2:0]VIL (1.8V Mode)0.45V
VIH (1.8V Mode)0.96
VIL (3.3V Mode)0.65
VIH (3.3V Mode)1.57
TJOperating junction temperature range-40140℃