JAJSIK5D February   2020  – February 2024 AWR2243

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 機能ブロック図
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Power-On Hours (POH)
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Power Supply Specifications
    6. 7.6 Power Consumption Summary
    7. 7.7 RF Specification
    8. 7.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 7.9 Timing and Switching Characteristics
      1. 7.9.1 Power Supply Sequencing and Reset Timing
      2. 7.9.2 Synchronized Frame Triggering
      3. 7.9.3 Input Clocks and Oscillators
        1. 7.9.3.1 Clock Specifications
      4. 7.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.9.4.1 Peripheral Description
          1. 7.9.4.1.1 SPI Timing Conditions
          2. 7.9.4.1.2 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. 7.9.4.1.3 SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 7.9.4.2 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 7.9.5 Inter-Integrated Circuit Interface (I2C)
        1. 7.9.5.1 I2C Timing Requirements
      6. 7.9.6 LVDS Interface Configuration
        1. 7.9.6.1 LVDS Interface Timings
      7. 7.9.7 General-Purpose Input/Output
        1. 7.9.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 7.9.8 Camera Serial Interface (CSI)
        1. 7.9.8.1 CSI Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Host Interface
    4. 8.4 Other Subsystems
      1. 8.4.1 ADC Data Format Over CSI2 Interface
      2. 8.4.2 ADC Channels (Service) for User Application
        1. 8.4.2.1 GPADC Parameters
  10. 9 Monitoring and Diagnostic Mechanisms
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short-, Medium-, and Long-Range Radar
    3. 10.3 Imaging Radar using Cascade Configuration
    4. 10.4 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Export Control Notice
    8. 11.8 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

5 Device Comparison

Table 5-1 Device Features Comparison
FUNCTION AWR2243(1) AWR1243 AWR1443 AWR1642 AWR1843
Number of receivers 4 4 4 4 4
Number of transmitters 3(2) 3 3 2 3(2)
On-chip memory — — 576KB 1.5MB 2MB
Max I/F (Intermediate Frequency) (MHz)

20

 15 5 5 10
Max real/complex 2x sampling rate (Msps)

45

 37.5 12.5 12.5 25
Max complex 1x sampling rate (Msps) 22.5 18.75 6.25 6.25 12.5
Processor
MCU (R4F) — — Yes Yes Yes
DSP (C674x) — — — Yes Yes
Peripherals
Serial Peripheral Interface (SPI) ports 1 1 1 2 2
Quad Serial Peripheral Interface (QSPI) — — Yes Yes Yes
Inter-Integrated Circuit (I2C) interface 1 — 1 1 1
Controller Area Network (DCAN) interface — — Yes Yes Yes
CAN FD — — — Yes Yes
Trace — — — Yes Yes
PWM — — — Yes Yes
Hardware In Loop (HIL/DMM) — — — Yes Yes
GPADC Yes — Yes Yes Yes
LVDS/Debug(3) Yes Yes Yes Yes Yes
CSI2 Yes Yes — — —
Hardware accelerator — — Yes — Yes
1-V bypass mode Yes Yes Yes Yes Yes
Cascade (20-GHz sync) Yes — — — —
JTAG — — Yes Yes Yes
Number of Tx that can be simultaneously used(2) 3(2) 2 2 2 3(2)
Per chirp configurable Tx phase shifter Yes — — — Yes
Product status(4) PRODUCT PREVIEW (PP),
ADVANCE INFORMATION (AI),
or PRODUCTION DATA (PD)		 PD PD PD PD PD
(1) Developed for Functional Safety applications, the device supports hardware integrity up to ASIL-B. Refer to the related documentation for more details.
(2) 3 Tx Simultaneous operation is supported only in AWR1843 and AWR2243 with 1V LDO bypass and PA LDO disable mode. In this mode 1V supply needs to be fed on the VOUT PA pin.
(3) The LVDS interface is not a production interface and is only used for debug
(4) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.