JAJSIL5B February   2020  – October 2024 ADC12DJ1600-Q1 , ADC12QJ1600-Q1 , ADC12SJ1600-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  ADC12xJ1600-Q1: Electrical Characteristics: Power Consumption
    7. 5.7  ADC12xJ1600-Q1: Electrical Characteristics: AC Specifications
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Comparison
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
        4. 6.3.2.4 ADC Core
          1. 6.3.2.4.1 ADC Theory of Operation
          2. 6.3.2.4.2 ADC Core Calibration
          3. 6.3.2.4.3 Analog Reference Voltage
          4. 6.3.2.4.4 ADC Over-range Detection
          5. 6.3.2.4.5 Code Error Rate (CER)
      3. 6.3.3 Temperature Monitoring Diode
      4. 6.3.4 Timestamp
      5. 6.3.5 Clocking
        1. 6.3.5.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 6.3.5.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 6.3.5.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 6.3.5.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 6.3.5.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 6.3.5.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 6.3.6 JESD204C Interface
        1. 6.3.6.1  Transport Layer
        2. 6.3.6.2  Scrambler
        3. 6.3.6.3  Link Layer
        4. 6.3.6.4  8B/10B Link Layer
          1. 6.3.6.4.1 Data Encoding (8B/10B)
          2. 6.3.6.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 6.3.6.4.3 Code Group Synchronization (CGS)
          4. 6.3.6.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 6.3.6.4.5 Frame and Multiframe Monitoring
        5. 6.3.6.5  64B/66B Link Layer
          1. 6.3.6.5.1 64B/66B Encoding
          2. 6.3.6.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
            1. 6.3.6.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
              1. 6.3.6.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
              2. 6.3.6.5.2.1.2 Forward Error Correction (FEC) Mode
          3. 6.3.6.5.3 Initial Lane Alignment
          4. 6.3.6.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 6.3.6.6  Physical Layer
          1. 6.3.6.6.1 SerDes Pre-Emphasis
        7. 6.3.6.7  JESD204C Enable
        8. 6.3.6.8  Multi-Device Synchronization and Deterministic Latency
        9. 6.3.6.9  Operation in Subclass 0 Systems
        10. 6.3.6.10 Alarm Monitoring
          1. 6.3.6.10.1 Clock Upset Detection
          2. 6.3.6.10.2 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Low Power Mode and High Performance Mode
      2. 6.4.2 JESD204C Modes
        1. 6.4.2.1 JESD204C Transport Layer Data Formats
        2. 6.4.2.2 64B/66B Sync Header Stream Configuration
        3. 6.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 6.4.3 Power-Down Modes
      4. 6.4.4 Test Modes
        1. 6.4.4.1 Serializer Test-Mode Details
        2. 6.4.4.2 PRBS Test Modes
        3. 6.4.4.3 Clock Pattern Mode
        4. 6.4.4.4 Ramp Test Mode
        5. 6.4.4.5 Short and Long Transport Test Mode
          1. 6.4.4.5.1 Short Transport Test Pattern
        6. 6.4.4.6 D21.5 Test Mode
        7. 6.4.4.7 K28.5 Test Mode
        8. 6.4.4.8 Repeated ILA Test Mode
        9. 6.4.4.9 Modified RPAT Test Mode
      5. 6.4.5 Calibration Modes and Trimming
        1. 6.4.5.1 Foreground Calibration Mode
        2. 6.4.5.2 Background Calibration Mode
        3. 6.4.5.3 Low-Power Background Calibration (LPBG) Mode
      6. 6.4.6 Offset Calibration
      7. 6.4.7 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
      2. 6.5.2 SCS
      3. 6.5.3 SCLK
      4. 6.5.4 SDI
      5. 6.5.5 SDO
      6. 6.5.6 Streaming Mode
      7. 6.5.7 SPI_Register_Map Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Analog Front-End Requirements
          2. 7.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 7.2.1.3 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 商標
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
7.2.1.2.2 Calculating Clock and SerDes Frequencies

The example LiDAR system uses four ADC channels running at 1 GSPS and the on-chip clock features of the device to reduce the system size and cost. The device is clocked by a 50-MHz crystal through the single-ended clock input (CLK_SE) and the integrated clock features are used to eliminate external clocking components. The internal PLL (C-PLL) generates the 1 GHz sampling clock for the ADC cores. The 50 MHz PLL reference is repeated through the PLLREFO output to the FPGA to generate the FPGA internal clocks including the application layer clock. The 50 MHz reference is divided down in the FPGA to generate the SYSREF signal which is sent to both the FPGA JESD204C core and to the device to achieve deterministic latency.

There are a number of clocking frequencies used in the example system shown in Figure 7-1. The reference clock frequency (fREF) is chosen by the designer and in this case is chosen as 50 MHz, which is the minimum supported reference frequency and which multiplies easily to 1 GHz. The sampling rate is set by the system requirements which is 1 GSPS (fS). The V, P and N dividers of the C-PLL are chosen as described in the Coverter PLL (C-PLL) section which, along with the reference frequency, determines the VCO frequency (fVCO). JMODE 8 was chosen to stay within the FPGA SerDes requirements (4 lanes, 12.5 Gbps max rate) which is a 64B/66B mode. TRIGOUT provides the FPGA SerDes PLL reference clock to the FPGA (fTRIGOUT) and PLLREFO provides the reference clock for the FPGA core logic. ORC (fORC) and ORD (fORD) provide additional clock outputs, if needed, for the FPGA or peripheral devices. SYSREF is generated within the FPGA and sent to the ADC in order to achieve deterministic latency. This is not usually recommended due to timing constraints, however the low reference frequency (50 MHz) significantly relaxes the SYSREF setup and hold timing and the SYSREF Windowing feature allows verification of proper capture timing of SYSREF relative to the reference clock. The SYSREF frequency must divide evenly into the reference clock frequency, in addition to meeting the JESD204 protocol requirements, in order to achieve deterministic latency due to the use of the C-PLL. The frequency and rate calculations are summarized in Table 7-2.

Table 7-2 Clock and SerDes Frequency Calculations for Example LiDAR Digitizer
ClockSymbolCalculationFrequency
Reference ClockfREFChosen by designer50 MHz
Sampling RatefSSystem requirement1 GSPS
C-PLL VCOfVCOfVCO = fSx P x V
where P is 2 and V is 4		8 GHz
SerDes LineratefLINERATEfLINERATE = fSx R
where R is 12.375 for JMODE 8
(see Table 6-16, Table 6-17 and Table 6-18)		12.375 Gbps / Lane (4 lanes)
TRIGOUT Clock OutputfTRIGOUTfTRIGOUT = fLINERATE/ RX_DIV
where RX_DIV is 32 (TRIGOUT_CTRL=0x81)		386.71875 MHz
SYSREFfSYSREFfSYSREF = fLINERATE/(66 x 32 x E x n)
where E is 3 for JMODE 8 (64B or 66B mode) and n is chosen such that fSYSREF is an integer division of
fREF (n = 5)		390.625 kHz
ORC Clock OutputfORCfORC = fREF/2 (See Table 6-5)25 MHz
ORD Clock OutputfORDfORD = fREF
(See Table 6-6)		50 MHz
FPGA Core ClockfFPGAfFPGA = fREF x M(1)(2)
where M is an integer value, chosen as 5		250 MHz (4 samples per cycle)
(1) In the clock configuration shown, the FPGA clock which runs the JESD204C core must be an integer multiplication of fREF in order to properly pass SYSREF from the reference clock domain to the core clock domain to achieve deterministic latency. In many cases the JESD204C IP may expect a clock rate of fLINERATE/66, which results in 187.5 MHz for the example. Some JESD204C IP cores may not allow the JESD204C clock frequency to deviate from this requirement and therefore IP provider should be consulted. If the requirement described for the FPGA core clock cannot be met than deterministic latency cannot be achieved (operation without deterministic latency is still supported).
(2) If the application layer runs at a different clock rate than the JESD204C core, then some logic may be needed to pass data between clock domains while maintain timing information. Further, many JESD204C IP cores output 64 bits per clock cycle which may include fractions of a sample (such as in JMODE 8) and therefore gearbox logic may be needed to transition to the desired sample rate.