The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency compensation circuits shown in Figure 8-10. In Type 2A, one additional high-frequency pole is added to attenuate high-frequency noise.

The following design guidelines are provided for advanced users who prefer to compensate using the general method.

The general design guidelines for device loop compensation are as follows:

1. Determine the crossover frequency f_co. A good starting point is one-tenth of the switching frequency, ƒ_SW.
2. R₃ can be determined by:
   Equation 19.

   where gm_ea is the transconductance of the error amplifier (1800 μS), gm_ps is the transconductance of the power stage (40 S) and VREF is the reference voltage (0.604 V).

3. Place a compensation zero at the dominant pole calculated in Equation 20 using C₁ and R₃.
   C₁ can be determined by Equation 21.
   Equation 20.
   Equation 21.
4. C₂ is optional. It can be used to cancel the zero from the equivalent series resistance (ESR) of the output capacitor C_OUT.
   Equation 22.