JAJSJ18A June   2024  – October 2024 LMH1229 , LMH1239

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements for Serial Management (SM) Bus Interface
    7. 5.7 Timing Requirements for Serial Parallel Interface (SPI) Interface
    8. 5.8 Typical Characteristics
      1. 5.8.1 TX Characteristics
      2. 5.8.2 RX Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Level Input Pins and Thresholds
      2. 6.3.2 Input and Output Signal Flow Control
        1. 6.3.2.1 Input Mux Selection (LMH1239 Only)
        2. 6.3.2.2 Output Mux and SDI_OUT Selection
      3. 6.3.3 Input Carrier Detect
      4. 6.3.4 Adaptive Cable Equalizer (SDI_IN±, SDI_IN1±)
      5. 6.3.5 Clock and Data (CDR) Recovery
      6. 6.3.6 CDR Loop Bandwidth Control
      7. 6.3.7 Output Function Control
      8. 6.3.8 Output Driver Control
        1. 6.3.8.1 Line-Side 75Ω Output Cable Driver (SDI_OUT±)
          1. 6.3.8.1.1 Output Amplitude (VOD)
          2. 6.3.8.1.2 Output Pre-Emphasis
          3. 6.3.8.1.3 Output Slew Rate
          4. 6.3.8.1.4 Output Polarity Inversion
        2. 6.3.8.2 Host-Side 100Ω Output Driver (OUT0±, OUT1±)
      9. 6.3.9 Debug and Diagnostic Features
        1. 6.3.9.1 Internal Eye Opening Monitor (EOM)
        2. 6.3.9.2 PRBS Generator, Error Checker, and Error Injector
        3. 6.3.9.3 Status Indicators and Interrupts
          1. 6.3.9.3.1 LOCK_N (Lock Indicator)
          2. 6.3.9.3.2 CD_N (Carrier Detect)
          3. 6.3.9.3.3 Cable Fault Detection (SDI_OUT+ Only)
          4. 6.3.9.3.4 INT_N (Interrupt)
        4. 6.3.9.4 Additional Programmability
          1. 6.3.9.4.1 Cable EQ Index (CEI)
          2. 6.3.9.4.2 Digital MUTEREF
    4. 6.4 Device Functional Modes
      1. 6.4.1 System Management Bus (SMBus) Mode
        1. 6.4.1.1 SMBus Read and Write Transaction
          1. 6.4.1.1.1 SMBus Write Operation Format
          2. 6.4.1.1.2 SMBus Read Operation Format
      2. 6.4.2 Serial Peripheral Interface (SPI) Mode
        1. 6.4.2.1 SPI Read and Write Transactions
          1. 6.4.2.1.1 SPI Write Transaction Format
          2. 6.4.2.1.2 SPI Read Transaction Format
        2. 6.4.2.2 SPI Daisy Chain
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 SMPTE Requirements and Specifications
      2. 7.1.2 Optimizing the Time to Adapt and Lock
      3. 7.1.3 Optimized Loop Bandwidth Settings for Diagnostic or Cascade Applications
      4. 7.1.4 LMH1229 and LMH1297 (EQ Mode) Pin-to-Pin Compatibility
    2. 7.2 Typical Application
      1. 7.2.1 Cable Equalizer With Loop-Through
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Cable Equalizer With Redundant SDI Input (LMH1239 only)
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Board Stack-Up and Ground References
        2. 7.4.1.2 High-Speed PCB Trace Routing and Coupling
          1. 7.4.1.2.1 SDI_IN± and SDI_OUT±:
          2. 7.4.1.2.2 OUT0± and OUT1±:
        3. 7.4.1.3 Anti-Pads
        4. 7.4.1.4 BNC Connector Layout and Routing
        5. 7.4.1.5 Power Supply and Ground Connections
        6. 7.4.1.6 Footprint Recommendations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.1.1 Design Requirements

For general LMH12x9 design requirements, reference the guidelines in Table 7-2.

For cable equalizer with loop-through application-specific requirements, reference the guidelines in Table 7-3.

Table 7-2 General Design Requirements
DESIGN PARAMETER REQUIREMENTS
SDI_IN+, SDI_IN1+ (LMH1239 only), SDI_OUT+ AC-coupling capacitors 4.7μF 0402 surface mount ceramic capacitors recommended.
SDI_IO–, SDI_IN1– (LMH1239 only), SDI_OUT– AC-coupling capacitors 4.7μF 0402 surface mount ceramic capacitors recommended, AC terminated with 75Ω to VSS. Negative polarity can be used if positive polarity is AC terminated with 75Ω to VSS.
OUT0± and OUT1± AC-coupling capacitors 4.7μF 0402 surface mount ceramic capacitors recommended.
Input and output terminations Input and output terminations provided internally. Do not add external terminations.
High-speed OUT0± and OUT1± trace impedance Route the OUT0± and OUT1± with coupled board traces and100Ω differential impedance.
SMPTE return loss Place BNC within 1 inch of the LMH12x9 and consult BNC vendor for recommended BNC landing pattern to meet SMPTE requirements.
SDI_IN+ and SDI_OUT+ crosstalk When a long length coax cable is connected to SDI_IN+, the signal amplitude at SDI_IN+ can be just a few mVpp. Layout precautions must be taken to minimize crosstalk from adjacent devices or from adjacent output port SDI_OUT+. To reduce cross coupling effects, keep SDI_OUT+ traces as far from SDI_IN+ as possible. When SDI_OUT+ is not used, TI recommends to turn off the output (SDI_OUT_SEL = H) for best results.
Note: When using the LMH1239, the same design requirements are applicable for SDI_IN1+ and SDI_OUT+ too.
DC power supply decoupling capacitors 10μF and 1μF bulk capacitors: place close to each device.
0.1μF capacitor: place close to each supply pin.
VDD_LDO decoupling capacitors 1μF and 0.1μF capacitors: place as close as possible to the device VDD_LDO pin. Do not use VDD_LDO as a 1.8V power supply source to external components.
MODE_SEL Pin SPI: Leave MODE_SEL unconnected (Level F)
SMBus: Connect 1kΩ to VSS (Level L)
Input SDI Reclocked Data Rate 11.88Gbps, 5.94Gbps, 2.97Gbps, 1.485Gbps, or Divide-by-1.001 sub-rates and 270Mbps. For all other input data rates, the reclocker is automatically bypassed.
Table 7-3 Cable Equalizer with Loop-Through Requirements
DESIGN PARAMETER REQUIREMENTS
OUT_MUX_SEL Pin 1kΩ to VSS (Level L) or float (Level F) to enable OUT0± only.
20kΩ to VSS (Level R) to enable both OUT0± and OUT1±.
LOOP_BW_SEL Pin 1kΩ to VIN (Level H) or float (Level F) for default CDR loop bandwidth operation (no external capacitor on LF±).
20kΩ to VSS (Level R) or 1kΩ to VSS (Level L) for decreased loop bandwidth (external capacitor required on LF±).
SDI_OUT_SEL Pin 1 kΩ to VSS (Level L) to enable cable loop-through SDI_OUT.
1 kΩ to VIN (Level H) to disable cable loop-through SDI_OUT.