JAJSJ45B April 2020 – July 2022 IWR6843AOP
PRODUCTION DATA
BALL NUMBER [1] | BALL NAME [2] | SIGNAL NAME [3] | PINCNTL ADDRESS[4] | MODE [5][9] | TYPE [6] | BALL RESET STATE [7] | PULL UP/DOWN TYPE [8] |
---|---|---|---|---|---|---|---|
M2 | GPIO_0 | GPIO_13 | 0xFFFFEA04 | 0 | IO | Output Disabled | Pull Down |
GPIO_0 | 1 | IO | |||||
PMIC_CLKOUT | 2 | O | |||||
ePWM1B | 10 | O | |||||
ePWM2A | 11 | O | |||||
L3 | GPIO_1 | GPIO_16 | 0xFFFFEA08 | 0 | IO | Output Disabled | Pull Down |
GPIO_1 | 1 | IO | |||||
SYNC_OUT | 2 | O | |||||
DMM_MUX_IN | 12 | I | |||||
SPIB_CS_N_1 | 13 | IO | |||||
SPIB_CS_N_2 | 14 | IO | |||||
EPWM1SYNCI | 15 | I | |||||
K3 | GPIO_2 | GPIO_26 | 0xFFFFEA64 | 0 | IO | Output Disabled | Pull Down |
GPIO_2 | 1 | IO | |||||
OSC_CLKOUT | 2 | O | |||||
MSS_UARTB_TX | 7 | O | |||||
BSS_UART_TX | 8 | O | |||||
SYNC_OUT | 9 | O | |||||
PMIC_CLKOUT | 10 | O | |||||
CHIRP_START | 11 | O | |||||
CHIRP_END | 12 | O | |||||
FRAME_START | 13 | O | |||||
U7 | GPIO_31 (DP0) | TRACE_DATA_0 | 0xFFFFEA7C | 0 | O | Output Disabled | Pull Down |
GPIO_31 | 1 | IO | |||||
DMM0 | 2 | I | |||||
MSS_UARTA_TX | 4 | IO | |||||
U6 | GPIO_32 (DP1) | TRACE_DATA_1 | 0xFFFFEA80 | 0 | O | Output Disabled | Pull Down |
GPIO_32 | 1 | IO | |||||
DMM1 | 2 | I | |||||
V5 | GPIO_33 (DP2) | TRACE_DATA_2 | 0xFFFFEA84 | 0 | O | Output Disabled | Pull Down |
GPIO_33 | 1 | IO | |||||
DMM2 | 2 | I | |||||
U5 | GPIO_34 (DP3) | TRACE_DATA_3 | 0xFFFFEA88 | 0 | O | Output Disabled | Pull Down |
GPIO_34 | 1 | IO | |||||
DMM3 | 2 | I | |||||
EPWM3SYNCO | 4 | O | |||||
V3 | GPIO_35 (DP4) | TRACE_DATA_4 | 0xFFFFEA8C | 0 | O | Output Disabled | Pull Down |
GPIO_35 | 1 | IO | |||||
DMM4 | 2 | I | |||||
EPWM2SYNCO | 4 | O | |||||
M1 | GPIO_36 (DP5) | TRACE_DATA_5 | 0xFFFFEA90 | 0 | O | Output Disabled | Pull Down |
GPIO_36 | 1 | IO | |||||
DMM5 | 2 | I | |||||
MSS_UARTB_TX | 5 | O | |||||
L2 | GPIO_37 (DP6) | TRACE_DATA_6 | 0xFFFFEA94 | 0 | O | Output Disabled | Pull Down |
GPIO_37 | 1 | IO | |||||
DMM6 | 2 | I | |||||
BSS_UART_TX | 5 | O | |||||
L1 | GPIO_38 (DP7) | TRACE_DATA_7 | 0xFFFFEA98 | 0 | O | Output Disabled | Pull Down |
GPIO_38 | 1 | IO | |||||
DMM7 | 2 | I | |||||
DSS_UART_TX | 5 | O | |||||
C3 | GPIO_39 (DP8) | TRACE_DATA_8 | 0xFFFFEA9C | 0 | O | Output Disabled | Pull Down |
GPIO_39 | 1 | IO | |||||
DMM8 | 2 | I | |||||
CAN_FD_TX | 4 | O | |||||
EPWM1SYNCI | 5 | I | |||||
B3 | GPIO_40 (DP9) | TRACE_DATA_9 | 0xFFFFEAA0 | 0 | O | Output Disabled | Pull Down |
GPIO_40 | 1 | IO | |||||
DMM9 | 2 | I | |||||
CAN_FD_RX | 4 | I | |||||
EPWM1SYNCO | 5 | O | |||||
C4 | GPIO_41 (DP10) | TRACE_DATA_10 | 0xFFFFEAA4 | 0 | O | Output Disabled | Pull Down |
GPIO_41 | 1 | IO | |||||
DMM10 | 2 | I | |||||
EPWM3A | 4 | O | |||||
A3 | GPIO_42 (DP11) | TRACE_DATA_11 | 0xFFFFEAA8 | 0 | O | Output Disabled | Pull Down |
GPIO_42 | 1 | IO | |||||
DMM11 | 2 | I | |||||
EPWM3B | 4 | O | |||||
B4 | GPIO_43 (DP12) | TRACE_DATA_12 | 0xFFFFEAAC | 0 | O | Output Disabled | Pull Down |
GPIO_43 | 1 | IO | |||||
DMM12 | 2 | I | |||||
EPWM1A | 4 | O | |||||
A4 | GPIO_44 (DP13) | TRACE_DATA_13 | 0xFFFFEAB0 | 0 | O | Output Disabled | Pull Down |
GPIO_44 | 1 | IO | |||||
DMM13 | 2 | I | |||||
EPWM1B | 4 | O | |||||
C5 | GPIO_45 (DP14) | TRACE_DATA_14 | 0xFFFFEAB4 | 0 | O | Output Disabled | Pull Down |
GPIO_45 | 1 | IO | |||||
DMM14 | 2 | I | |||||
EPWM2A | 4 | O | |||||
B5 | GPIO_46 (DP15) | TRACE_DATA_15 | 0xFFFFEAB8 | 0 | O | Output Disabled | Pull Down |
GPIO_46 | 1 | IO | |||||
DMM15 | 2 | I | |||||
EPWM2B | 4 | O | |||||
U3 | GPIO_47 (DMM_CLK) | TRACE_CLK | 0xFFFFEABC | 0 | O | Output Disabled | Pull Down |
GPIO_47 | 1 | IO | |||||
DMM_CLK | 2 | I | |||||
U4 | DMM_SYNC | TRACE_CTL | 0xFFFFEAC0 | 0 | O | Output Disabled | Pull Down |
DMM_SYNC | 2 | I | |||||
V13 | MCU_CLKOUT | GPIO_25 | 0xFFFFEA60 | 0 | IO | Output Disabled | Pull Down |
MCU_CLKOUT | 1 | O | |||||
CHIRP_START | 2 | O | |||||
CHIRP_END | 6 | O | |||||
FRAME_START | 7 | O | |||||
EPWM1A | 12 | O | |||||
U14 | NERROR_IN | NERROR_IN | 0xFFFFEA44 | 0 | I | Input | |
U15 | NERROR_OUT | NERROR_OUT | 0xFFFFEA4C | 0 | O | Hi-Z (Open Drain) | |
V10 | PMIC_CLKOUT | SOP[2] | 0xFFFFEA68 | During Power Up | I | Output Disabled | Pull Down |
GPIO_27 | 0 | IO | |||||
PMIC_CLKOUT | 1 | O | |||||
CHIRP_START | 6 | O | |||||
CHIRP_END | 7 | O | |||||
FRAME_START | 8 | O | |||||
EPWM1B | 11 | O | |||||
EPWM2A | 12 | O | |||||
H3 | QSPI[0] | GPIO_8 | 0xFFFFEA2C | 0 | IO | Output Disabled | Pull Down |
QSPI[0] | 1 | IO | |||||
SPIB_MISO | 2 | IO | |||||
G2 | QSPI[1] | GPIO_9 | 0xFFFFEA30 | 0 | IO | Output Disabled | Pull Down |
QSPI[1] | 1 | I | |||||
SPIB_MOSI | 2 | IO | |||||
SPIB_CS_N_2 | 8 | IO | |||||
J3 | QSPI[2] | GPIO_10 | 0xFFFFEA34 | 0 | IO | Output Disabled | Pull Down |
QSPI[2] | 1 | I | |||||
CAN_FD_TX | 8 | O | |||||
K2 | QSPI[3] | GPIO_11 | 0xFFFFEA38 | 0 | IO | Output Disabled | Pull Down |
QSPI[3] | 1 | I | |||||
CAN_FD_RX | 8 | I | |||||
H2 | QSPI_CLK | GPIO_7 | 0xFFFFEA3C | 0 | IO | Output Disabled | Pull Down |
QSPI_CLK | 1 | O | |||||
SPIB_CLK | 2 | IO | |||||
DSS_UART_TX | 6 | O | |||||
J2 | QSPI_CS_N | GPIO_6 | 0xFFFFEA40 | 0 | IO | Output Disabled | Pull Up |
QSPI_CS_N | 1 | O | |||||
SPIB_CS_N | 2 | IO | |||||
V16 | RS232_RX | GPIO_15 | 0xFFFFEA74 | 0 | IO | Input Enabled | Pull Up |
RS232_RX | 1 | I | |||||
MSS_UARTA_RX | 2 | I | |||||
BSS_UART_TX | 6 | IO | |||||
MSS_UARTB_RX | 7 | IO | |||||
CAN_FD_RX | 8 | I | |||||
I2C_SCL | 9 | IO | |||||
EPWM2A | 10 | O | |||||
EPWM2B | 11 | O | |||||
EPWM3A | 12 | O | |||||
U16 | RS232_TX | GPIO_14 | 0xFFFFEA78 | 0 | IO | Output Enabled | |
RS232_TX | 1 | O | |||||
MSS_UARTA_TX | 5 | IO | |||||
MSS_UARTB_TX | 6 | IO | |||||
BSS_UART_TX | 7 | IO | |||||
CAN_FD_TX | 10 | O | |||||
I2C_SDA | 11 | IO | |||||
EPWM1A | 12 | O | |||||
EPWM1B | 13 | O | |||||
NDMM_EN | 14 | I | |||||
EPWM2A | 15 | O | |||||
D2 | SPIA_CLK | GPIO_3 | 0xFFFFEA14 | 0 | IO | Output Disabled | Pull Up |
SPIA_CLK | 1 | IO | |||||
DSS_UART_TX | 7 | O | |||||
C2 | SPIA_CS_N | GPIO_30 | 0xFFFFEA18 | 0 | IO | Output Disabled | Pull Up |
SPIA_CS_N | 1 | IO | |||||
CAN_FD_TX | 6 | O | |||||
D1 | SPIA_MISO | GPIO_20 | 0xFFFFEA10 | 0 | IO | Output Disabled | Pull Up |
SPIA_MISO | 1 | IO | |||||
CAN_FD_TX | 2 | O | |||||
F2 | SPIA_MOSI | GPIO_19 | 0xFFFFEA0C | 0 | IO | Output Disabled | Pull Up |
SPIA_MOSI | 1 | IO | |||||
CAN_FD_RX | 2 | I | |||||
DSS_UART_TX | 8 | O | |||||
E2 | SPIB_CLK | GPIO_5 | 0xFFFFEA24 | 0 | IO | Output Disabled | Pull Up |
SPIB_CLK | 1 | IO | |||||
MSS_UARTA_RX | 2 | I | |||||
MSS_UARTB_TX | 6 | O | |||||
BSS_UART_TX | 7 | O | |||||
CAN_FD_RX | 8 | I | |||||
D3 | SPIB_CS_N | GPIO_4 | 0xFFFFEA28 | 0 | IO | Output Disabled | Pull Up |
SPIB_CS_N | 1 | IO | |||||
MSS_UARTA_TX | 2 | O | |||||
MSS_UARTB_TX | 6 | O | |||||
BSS_UART_TX | 7 | IO | |||||
QSPI_CLK_EXT | 8 | I | |||||
CAN_FD_TX | 9 | O | |||||
G3 | SPIB_MISO | GPIO_22 | 0xFFFFEA20 | 0 | IO | Output Disabled | Pull Up |
SPIB_MISO | 1 | IO | |||||
I2C_SCL | 2 | IO | |||||
DSS_UART_TX | 6 | O | |||||
G1 | SPIB_MOSI | GPIO_21 | 0xFFFFEA1C | 0 | IO | Output Disabled | Pull Up |
SPIB_MOSI | 1 | IO | |||||
I2C_SDA | 2 | IO | |||||
B2 | SPI_HOST_INTR | GPIO_12 | 0xFFFFEA00 | 0 | IO | Output Disabled | Pull Down |
SPI_HOST_INTR | 1 | O | |||||
SPIB_CS_N_1 | 6 | IO | |||||
U12 | SYNC_IN | GPIO_28 | 0xFFFFEA6C | 0 | IO | Output Disabled | Pull Down |
SYNC_IN | 1 | I | |||||
MSS_UARTB_RX | 6 | IO | |||||
DMM_MUX_IN | 7 | I | |||||
SYNC_OUT | 9 | O | |||||
M3 | SYNC_OUT | SOP[1] | 0xFFFFEA70 | During Power Up | I | Output Disabled | Pull Down |
GPIO_29 | 0 | IO | |||||
SYNC_OUT | 1 | O | |||||
DMM_MUX_IN | 9 | I | |||||
SPIB_CS_N_1 | 10 | IO | |||||
SPIB_CS_N_2 | 11 | IO | |||||
T3 | TCK | GPIO_17 | 0xFFFFEA50 | 0 | IO | Input Enabled | Pull Down |
TCK | 1 | I | |||||
MSS_UARTB_TX | 2 | O | |||||
CAN_FD_TX | 8 | O | |||||
U9 | TDI | GPIO_23 | 0xFFFFEA58 | 0 | IO | Input Enabled | Pull Up |
TDI | 1 | I | |||||
MSS_UARTA_RX | 2 | I | |||||
U10 | TDO | SOP[0] | 0xFFFFEA5C | During Power Up | I | Output Enabled | |
GPIO_24 | 0 | IO | |||||
TDO | 1 | O | |||||
MSS_UARTA_TX | 2 | O | |||||
MSS_UARTB_TX | 6 | O | |||||
BSS_UART_TX | 7 | O | |||||
NDMM_EN | 9 | I | |||||
U8 | TMS | GPIO_18 | 0xFFFFEA54 | 0 | IO | Input Enabled | Pull Down |
TMS | 1 | I | |||||
BSS_UART_TX | 2 | O | |||||
CAN_FD_RX | 6 | I | |||||
U13 | WARM_RESET | WARM_RESET | 0xFFFFEA48 | 0 | IO | Hi-Z Input (Open Drain) | |
R2 | LVDS_CLKM | LVDS_CLKM | O | ||||
R1 | LVDS_CLKP | LVDS_CLKP | O | ||||
N2 | LVDS_TXP[0] | LVDS_TXP[0] | O | ||||
N1 | LVDS_TXM[0] | LVDS_TXM[0] | O | ||||
P2 | LVDS_TXP[1] | LVDS_TXP[1] | O | ||||
P1 | LVDS_TXM[1] | LVDS_TXM[1] | O | ||||
T1 | LVDS_FRCLKP | LVDS_FRCLKP | O | ||||
T2 | LVDS_FRCLKM | LVDS_FRCLKM | O | ||||
U11 | NRESET | NRESET | I | ||||
A7 | CLKP | CLKP | I | ||||
B7 | CLKM | CLKM | I | ||||
A14 | OSC_CLKOUT | OSC_CLKOUT | O | ||||
A16 | VBGAP | VBGAP | O | ||||
E1 | VDDIN | VDDIN | PWR | ||||
J1 | VDDIN | VDDIN | PWR | ||||
V4 | VDDIN | VDDIN | PWR | ||||
V8 | VDDIN | VDDIN | PWR | ||||
V15 | VDDIN | VDDIN | PWR | ||||
A5 | VIN_SRAM | VIN_SRAM | PWR | ||||
V6 | VIN_SRAM | VIN_SRAM | PWR | ||||
V12 | VIN_SRAM | VIN_SRAM | PWR | ||||
C1 | VNWA | VNWA | PWR | ||||
V7 | VNWA | VNWA | PWR | ||||
V14 | VNWA | VNWA | PWR | ||||
H1 | VIOIN | VIOIN | PWR | ||||
V9 | VIOIN | VIOIN | PWR | ||||
B1 | VIOIN_18 | VIOIN_18 | PWR | ||||
F1 | VIOIN_18 | VIOIN_18 | PWR | ||||
K1 | VIOIN_18 | VIOIN_18 | PWR | ||||
V11 | VIOIN_18 | VIOIN_18 | PWR | ||||
C15 | VIN_18CLK | VIN_18CLK | PWR | ||||
C18 | VIN_18CLK | VIN_18CLK | PWR | ||||
U2 | VIOIN_18DIFF | VIOIN_18DIFF | PWR | ||||
V2 | VPP | VPP | PWR | ||||
J16 | VIN_13RF1 | VIN_13RF1 | PWR | ||||
J17 | VIN_13RF1 | VIN_13RF1 | PWR | ||||
J18 | VIN_13RF1 | VIN_13RF1 | PWR | ||||
H16 | VIN_13RF2 | VIN_13RF2 | PWR | ||||
H17 | VIN_13RF2 | VIN_13RF2 | PWR | ||||
H18 | VIN_13RF2 | VIN_13RF2 | PWR | ||||
M16 | VIN_18BB | VIN_18BB | PWR | ||||
M17 | VIN_18BB | VIN_18BB | PWR | ||||
M18 | VIN_18BB | VIN_18BB | PWR | ||||
A12 | VIN_18VCO | VIN_18VCO | PWR | ||||
C11 | VIN_18VCO | VIN_18VCO | PWR | ||||
A1 | VSS | VSS | GND | ||||
A2 | VSS | VSS | GND | ||||
E3 | VSS | VSS | GND | ||||
F3 | VSS | VSS | GND | ||||
N3 | VSS | VSS | GND | ||||
P3 | VSS | VSS | GND | ||||
R3 | VSS | VSS | GND | ||||
T4 | VSS | VSS | GND | ||||
T5 | VSS | VSS | GND | ||||
T6 | VSS | VSS | GND | ||||
T7 | VSS | VSS | GND | ||||
T8 | VSS | VSS | GND | ||||
T9 | VSS | VSS | GND | ||||
T10 | VSS | VSS | GND | ||||
T11 | VSS | VSS | GND | ||||
T12 | VSS | VSS | GND | ||||
T13 | VSS | VSS | GND | ||||
T14 | VSS | VSS | GND | ||||
T15 | VSS | VSS | GND | ||||
T16 | VSS | VSS | GND | ||||
U1 | VSS | VSS | GND | ||||
V1 | VSS | VSS | GND | ||||
A6 | VSSA | VSSA | GND | ||||
A8 | VSSA | VSSA | GND | ||||
A11 | VSSA | VSSA | GND | ||||
A13 | VSSA | VSSA | GND | ||||
A15 | VSSA | VSSA | GND | ||||
A17 | VSSA | VSSA | GND | ||||
A18 | VSSA | VSSA | GND | ||||
B6 | VSSA | VSSA | GND | ||||
B8 | VSSA | VSSA | GND | ||||
B9 | VSSA | VSSA | GND | ||||
B10 | VSSA | VSSA | GND | ||||
B11 | VSSA | VSSA | GND | ||||
B12 | VSSA | VSSA | GND | ||||
B13 | VSSA | VSSA | GND | ||||
B14 | VSSA | VSSA | GND | ||||
B15 | VSSA | VSSA | GND | ||||
B16 | VSSA | VSSA | GND | ||||
B17 | VSSA | VSSA | GND | ||||
B18 | VSSA | VSSA | GND | ||||
C6 | VSSA | VSSA | GND | ||||
C7 | VSSA | VSSA | GND | ||||
C8 | VSSA | VSSA | GND | ||||
C12 | VSSA | VSSA | GND | ||||
C13 | VSSA | VSSA | GND | ||||
C14 | VSSA | VSSA | GND | ||||
C16 | VSSA | VSSA | GND | ||||
C17 | VSSA | VSSA | GND | ||||
D16 | VSSA | VSSA | GND | ||||
D17 | VSSA | VSSA | GND | ||||
D18 | VSSA | VSSA | GND | ||||
E16 | VSSA | VSSA | GND | ||||
E17 | VSSA | VSSA | GND | ||||
E18 | VSSA | VSSA | GND | ||||
F16 | VSSA | VSSA | GND | ||||
F17 | VSSA | VSSA | GND | ||||
F18 | VSSA | VSSA | GND | ||||
K16 | VSSA | VSSA | GND | ||||
K17 | VSSA | VSSA | GND | ||||
K18 | VSSA | VSSA | GND | ||||
L16 | VSSA | VSSA | GND | ||||
L17 | VSSA | VSSA | GND | ||||
L18 | VSSA | VSSA | GND | ||||
N16 | VSSA | VSSA | GND | ||||
N17 | VSSA | VSSA | GND | ||||
N18 | VSSA | VSSA | GND | ||||
P16 | VSSA | VSSA | GND | ||||
R16 | VSSA | VSSA | GND | ||||
R17 | VSSA | VSSA | GND | ||||
T17 | VSSA | VSSA | GND | ||||
U17 | VSSA | VSSA | GND | ||||
U18 | VSSA | VSSA | GND | ||||
V17 | VSSA | VSSA | GND | ||||
V18 | VSSA | VSSA | GND | ||||
A10 | VOUT_14APLL | VOUT_14APLL | O | ||||
A9 | VOUT_14SYNTH | VOUT_14SYNTH | O | ||||
G16 | VOUT_PA | VOUT_PA | IO | ||||
G17 | VOUT_PA | VOUT_PA | IO | ||||
G18 | VOUT_PA | VOUT_PA | IO | ||||
P18 | Analog Test1 / GPADC1 | Analog Test1 / GPADC1 | IO | ||||
P17 | Analog Test2 / GPADC2 | Analog Test2 / GPADC2 | IO | ||||
R18 | Analog Test3 / GPADC3 | Analog Test3 / GPADC3 | IO | ||||
T18 | Analog Test4 / GPADC4 | Analog Test4 / GPADC4 | IO | ||||
C9 | ANAMUX / GPADC5 | ANAMUX / GPADC5 | IO | ||||
C10 | VSENSE / GPADC6 | VSENSE / GPADC6 | IO |
The following list describes the table column headers:
IO MUX registers are available in the MSS memory map and the respective mapping to device pins is as follows:
Default Pin/Ball Name | Package Ball /Pin (Address) | Pin Mux Config Register |
---|---|---|
SPI_HOST_INTR | B2 | 0xFFFFEA00 |
GPIO_0 | M2 | 0xFFFFEA04 |
GPIO_1 | L3 | 0xFFFFEA08 |
SPIA_MOSI | F2 | 0xFFFFEA0C |
SPIA_MISO | D1 | 0xFFFFEA10 |
SPIA_CLK | D2 | 0xFFFFEA14 |
SPIA_CS_N | C2 | 0xFFFFEA18 |
SPIB_MOSI | G1 | 0xFFFFEA1C |
SPIB_MISO | G3 | 0xFFFFEA20 |
SPIB_CLK | E2 | 0xFFFFEA24 |
SPIB_CS_N | D3 | 0xFFFFEA28 |
QSPI[0] | H3 | 0xFFFFEA2C |
QSPI[1] | G2 | 0xFFFFEA30 |
QSPI[2] | J3 | 0xFFFFEA34 |
QSPI[3] | K2 | 0xFFFFEA38 |
QSPI_CLK | H2 | 0xFFFFEA3C |
QSPI_CS_N | J2 | 0xFFFFEA40 |
NERROR_IN | U14 | 0xFFFFEA44 |
WARM_RESET | U13 | 0xFFFFEA48 |
NERROR_OUT | U15 | 0xFFFFEA4C |
TCK | T3 | 0xFFFFEA50 |
TMS | U8 | 0xFFFFEA54 |
TDI | U9 | 0xFFFFEA58 |
TDO | U10 | 0xFFFFEA5C |
MCU_CLKOUT | V13 | 0xFFFFEA60 |
GPIO_2 | K3 | 0xFFFFEA64 |
PMIC_CLKOUT | V10 | 0xFFFFEA68 |
SYNC_IN | U12 | 0xFFFFEA6C |
SYNC_OUT | M3 | 0xFFFFEA70 |
RS232_RX | V16 | 0xFFFFEA74 |
RS232_TX | U16 | 0xFFFFEA78 |
GPIO_31 | U7 | 0xFFFFEA7C |
GPIO_32 | U6 | 0xFFFFEA80 |
GPIO_33 | V5 | 0xFFFFEA84 |
GPIO_34 | U5 | 0xFFFFEA88 |
GPIO_35 | V3 | 0xFFFFEA8C |
GPIO_36 | M1 | 0xFFFFEA90 |
GPIO_37 | L2 | 0xFFFFEA94 |
GPIO_38 | L1 | 0xFFFFEA98 |
GPIO_39 | C3 | 0xFFFFEA9C |
GPIO_40 | B3 | 0xFFFFEAA0 |
GPIO_41 | C4 | 0xFFFFEAA4 |
GPIO_42 | A3 | 0xFFFFEAA8 |
GPIO_43 | B4 | 0xFFFFEAAC |
GPIO_44 | A4 | 0xFFFFEAB0 |
GPIO_45 | C5 | 0xFFFFEAB4 |
GPIO_46 | B5 | 0xFFFFEAB8 |
GPIO_47 | U3 | 0xFFFFEABC |
DMM_SYNC | U4 | 0xFFFFEAC0 |
The register layout is as follows:
BIT | FIELD | TYPE | RESET (POWER ON DEFAULT) | DESCRIPTION |
---|---|---|---|---|
31-11 | NU | RW | 0 | Reserved |
10 | SC | RW | 0 | IO slew rate
control: 0 = Higher slew rate 1 = Lower slew rate |
9 | PUPDSEL | RW | 0 | Pullup/PullDown
Selection 0 = Pull Down 1 = Pull Up (This field is valid only if Pull Inhibit is set as '0') |
8 | PI | RW | 0 | Pull Inhibit/Pull
Disable 0 = Enable 1 = Disable |
7 | OE_OVERRIDE | RW | 1 | Output Override |
6 | OE_OVERRIDE_CTRL | RW | 1 | Output Override
Control: (A '1' here overrides any o/p manipulation of this IO by any of the peripheral block hardware it is associated with for example a SPI Chip select) |
5 | IE_OVERRIDE | RW | 0 | Input Override |
4 | IE_OVERRIDE_CTRL | RW | 0 | Input Override
Control: (A '1' here overrides any i/p value on this IO with a desired value) |
3-0 | FUNC_SEL | RW | 1 | Function select for Pin Multiplexing (Refer to the Pin Mux Sheet) |