JAJSJG4B August   2020  – May 2024 LP8864S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Logic Interface Characteristics
    7. 5.7 Timing Requirements for I2C Interface
    8.     14
    9. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Control Interface
      2. 6.3.2 Function Setting
      3. 6.3.3 Device Supply (VDD)
      4. 6.3.4 Enable (EN)
      5. 6.3.5 Charge Pump
      6. 6.3.6 Boost Controller
        1. 6.3.6.1 Boost Cycle-by-Cycle Current Limit
        2. 6.3.6.2 Controller Min On/Off Time
        3. 6.3.6.3 Boost Adaptive Voltage Control
          1. 6.3.6.3.1 FB Divider Using Two-Resistor Method
          2. 6.3.6.3.2 FB Divider Using Three-Resistor Method
          3. 6.3.6.3.3 FB Divider Using External Compensation
        4. 6.3.6.4 Boost Sync and Spread Spectrum
        5. 6.3.6.5 Boost Output Discharge
        6. 6.3.6.6 Light Load Mode
      7. 6.3.7 LED Current Sinks
        1. 6.3.7.1 LED Output Current Setting
        2. 6.3.7.2 LED Output String Configuration
        3. 6.3.7.3 LED Output PWM Clock Generation
      8. 6.3.8 Brightness Control
        1. 6.3.8.1 Brightness Control Signal Path
        2. 6.3.8.2 Dimming Mode
        3. 6.3.8.3 LED Dimming Frequency
        4. 6.3.8.4 Phase-Shift PWM Mode
        5. 6.3.8.5 Hybrid Mode
        6. 6.3.8.6 Direct PWM Mode
        7. 6.3.8.7 Sloper
        8. 6.3.8.8 PWM Detector Hysteresis
        9. 6.3.8.9 Dither
      9. 6.3.9 Protection and Fault Detections
        1. 6.3.9.1 Supply Faults
          1. 6.3.9.1.1 VIN Undervoltage Faults (VINUVLO)
          2. 6.3.9.1.2 VIN Overvoltage Faults (VINOVP)
          3. 6.3.9.1.3 VDD Undervoltage Faults (VDDUVLO)
          4. 6.3.9.1.4 VIN OCP Faults (VINOCP)
            1. 6.3.9.1.4.1 VIN OCP Current Limit vs. Boost Cycle-by-Cycle Current Limit
          5. 6.3.9.1.5 Charge Pump Faults (CPCAP, CP)
          6. 6.3.9.1.6 CRC Error Faults (CRCERR)
        2. 6.3.9.2 Boost Faults
          1. 6.3.9.2.1 Boost Overvoltage Faults (BSTOVPL, BSTOVPH)
          2. 6.3.9.2.2 Boost Overcurrent Faults (BSTOCP)
          3. 6.3.9.2.3 LEDSET Resistor Missing Faults (LEDSET)
          4. 6.3.9.2.4 MODE Resistor Missing Faults (MODESEL)
          5. 6.3.9.2.5 FSET Resistor Missing Faults (FSET)
          6. 6.3.9.2.6 ISET Resistor Out of Range Faults (ISET)
          7. 6.3.9.2.7 Thermal Shutdown Faults (TSD)
        3. 6.3.9.3 LED Faults
          1. 6.3.9.3.1 Open LED Faults (OPEN_LED)
          2. 6.3.9.3.2 Short LED Faults (SHORT_LED)
          3. 6.3.9.3.3 LED Short to GND Faults (GND_LED)
          4. 6.3.9.3.4 Invalid LED String Faults (INVSTRING)
          5. 6.3.9.3.5 I2C Timeout Faults
        4. 6.3.9.4 Overview of the Fault and Protection Schemes
    4. 6.4 Device Functional Modes
      1. 6.4.1  State Diagram
      2. 6.4.2  Shutdown
      3. 6.4.3  Device Initialization
      4. 6.4.4  Standby Mode
      5. 6.4.5  Power-line FET Soft Start
      6. 6.4.6  Boost Start-Up
      7. 6.4.7  Normal Mode
      8. 6.4.8  Fault Recovery
      9. 6.4.9  Latch Fault
      10. 6.4.10 Start-Up Sequence
    5. 6.5 Programming
      1. 6.5.1 I2C-Compatible Interface
      2. 6.5.2 Programming Examples
        1. 6.5.2.1 General Configuration Registers
        2. 6.5.2.2 Clearing Fault Interrupts
        3. 6.5.2.3 Disabling Fault Interrupts
        4. 6.5.2.4 Diagnostic Registers
  8. 7 Register Maps
    1. 7.1 FullMap Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Full Feature Application for Display Backlight
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Inductor Selection
          2. 8.2.1.2.2  Output Capacitor Selection
          3. 8.2.1.2.3  Input Capacitor Selection
          4. 8.2.1.2.4  Charge Pump Output Capacitor
          5. 8.2.1.2.5  Charge Pump Flying Capacitor
          6. 8.2.1.2.6  Output Diode
          7. 8.2.1.2.7  Switching FET
          8. 8.2.1.2.8  Boost Sense Resistor
          9. 8.2.1.2.9  Power-Line FET
          10. 8.2.1.2.10 Input Current Sense Resistor
          11. 8.2.1.2.11 Feedback Resistor Divider
          12. 8.2.1.2.12 Critical Components for Design
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Application with Basic/Minimal Operation
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 SEPIC Mode Application
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1  Inductor Selection
          2. 8.2.3.2.2  Coupling Capacitor Selection
          3. 8.2.3.2.3  Output Capacitor Selection
          4. 8.2.3.2.4  Input Capacitor Selection
          5. 8.2.3.2.5  Charge Pump Output Capacitor
          6. 8.2.3.2.6  Charge Pump Flying Capacitor
          7. 8.2.3.2.7  Switching FET
          8. 8.2.3.2.8  Output Diode
          9. 8.2.3.2.9  Switching Sense Resistor
          10. 8.2.3.2.10 Power-Line FET
          11. 8.2.3.2.11 Input Current Sense Resistor
          12. 8.2.3.2.12 Feedback Resistor Divider
          13. 8.2.3.2.13 Critical Components for Design
        3. 8.2.3.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

Limits apply over the full operation temperature range –40°C ≤TA ≤ +125°C , unless otherwise speicified. VIN = 12V, VDD = 3.3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General Electrical Characteristics
IQ Shutdown mode current, VDD pin EN = L 1 5 µA
IQ Active mode current, VDD pin(1) FSW = 303 kHz, PWM = H, BOOST-FET IPD25N06S4L-30, Charge Pump Disabled 15 65 mA
IQ Active mode current, VDD pin(1) FSW = 2200 kHz, PWM = H, BOOST-FET IPD25N06S4L-30, Charge Pump Disabled 40 75 mA
IQ Active mode current, VDD pin(1) FSW = 303 kHz, PWM = H, BOOST-FET IPD25N06S4L-30, Charge Pump Enabled 20 91 mA
IQ Active mode current, VDD pin(1) FSW = 2200 kHz, PWM = H, BOOST-FET IPD25N06S4L-30, Charge Pump Enabled 65 104 mA
CPUMP and LDO Electrical Characteristics
VCPUMP Voltage accuracy VDD = 3.0 to 3.6V; ILOAD = 1 to 50mA 4.8 5 5.2 V
fCP CP switching frequency 387 417 447 kHz
VCPUMP_UVLO VCPUMP UVLO threshold VCPUMP falling edge 3.95 4.2 4.4 V
VCPUMP_UVLO VCPUMP UVLO threshold VCPUMP rising edge 4.15 4.4 4.6 V
VCPUMP_HYS VCPUMP UVLO hysteresis 0.1 0.2 V
TSTART_UP Charge pump startup time CCPUMP = 10µF 1000 2000 µs
Protection Electrical Characteristics
VDDUVLO_F VDD UVLO threshold VDD falling 2.68 2.8 2.92 V
VDDUVLO_R VDD UVLO threshold VDD rising 3.0 V
VDDUVLO_H VDD UVLO hysteresis 0.1 V
VINUVLO_TH UVLO pin threshold VUVLO falling 0.753 0.777 0.801 V
IUVLO UVLO pin bias current VUVLO = VUVLO_TH + 50mV –5 µA
VINOVP_TH OVP threshold VSENSE_P rising 40.8 43 45.2 V
VINOVP_HYS OVP hysteresis 1.7 V
VINOCP_TH Input OCP threshold RISENSE = 20mΩ 187 220 253 mV
TSD Thermal shutdown threshold(1) Temperature rising 150 165 180 °C
TSD Thermal shutdown hysteresis(1) 20 °C
ISD_LEAKAGE SD leakage current VSD = 48V 1 µA
ISD SD pull down current RSD = 20kΩ 250 325 400 µA
VFB_OVPL FB pin - Boost OVP low threshold 1.423 V
VFB_OVPH FB pin - Boost OVP high threshold 1.76 V
VFB_UVP FB pin - Boost OCP threshold 0.886 V
VBST_OVPH Discharge pin - Boost OVP high threshold 48.5 50 51.8 V
Input PWM Electrical Characteristics
IPWM_LEAKAGE PWM leakage current VPWM = 5V 1 µA
fPWM_IN PWM input frequency 100 20000 Hz
tPWM_MIN_ON PWM input minimum on-time Direct PWM mode 200 ns
tPWM_MIN_ON PWM input minimum on-time Phase Shift PWM mode,  Hybrid mode, Current Dimming mode 200 220 ns
PWM_INRES PWM input resolution fPWM_IN = 100Hz 16 bit
PWM_INRES PWM input resolution fPWM_IN = 20kHz 10 bit
LED Current Sink and LED PWM Electrical Characteristics
ILEAKAGE Leakage current on OUTx OUTx = VOUT = 45V, EN= L 0.1 2.5 µA
VISET ISET voltage 1.17 1.21 1.25 V
IMAX Maximum LED sink current OUTx 200 mA
VISET_UVLO ISET pin undervoltage 0.97 1 1.03 V
RISET ISET Resistor range IOUT = 30mA to 200mA 15.6 104 kΩ
ILED_LIMIT LED current limit when ISET pin short to GND 280 mA
IACC LED sink current accuracy RISET = 15.6kΩ, IOUT = 150mA, PWM = 100% -4 4 %
IMATCH LED sink current matching RISET = 15.6kΩ, IOUT = 150mA, PWM = 100% 1 3.5 %
fDIM LED dimming frequency PWM_FSET =3.92kΩ 141 152 163 Hz
fDIM LED dimming frequency PWM_FSET =4.75kΩ 283 305 327
fDIM LED dimming frequency PWM_FSET =5.76kΩ 567 610 653
fDIM LED dimming frequency PWM_FSET =7.87kΩ 1135 1221 1307
fDIM LED dimming frequency PWM_FSET =11kΩ 2270 2441 2612
fDIM LED dimming frequency PWM_FSET =17.8kΩ 4541 4883 5225
fDIM LED dimming frequency PWM_FSET =42.4kΩ 9082 9766 10450
fDIM LED dimming frequency PWM_FSET =124kΩ 18163 19531 20899
DIM Dimming ratio fPWM_OUT = 152Hz 32000:1
DIM Dimming ratio fPWM_OUT = 4.88kHz 1000:1
VHEADROOM LED sink headroom 0.7 V
VHEADROOM_HYS LED sink headroom hysteresis 0.8 V
VLEDSHORT LED internal short threshold 5.4 V
VSHORTGND LED short to ground threshold 0.24 V
tPWM_OUT LED output minimum pulse 200 ns
Boost Converter Electrical Characteristics
fSW Switching Frequency BST_FSET =7.87kΩ 93 100 107 kHz
fSW Switching Frequency BST_FSET =4.75kΩ 186 200 214 kHz
fSW Switching Frequency BST_FSET =5.76kΩ 281 303 325 kHz
fSW Switching Frequency BST_FSET =3.92kΩ  372 400 428 kHz
fSW Switching Frequency BST_FSET =11kΩ 465 500 535 kHz
fSW Switching Frequency BST_FSET =17.8kΩ 1690 1818 1946 kHz
fSW Switching Frequency BST_FSET =42.4kΩ 1860 2000 2140 kHz
fSW Switching Frequency BST_FSET =124kΩ 2066 2222 2378 kHz
VISNS External FET current limit VISNS threshold, RSENSE = 15 to 50mΩ 180 200 220 mV
ISEL_MAX IDAC maximum current VDD = 3.3V 36.4 38.7 40.2 µA
RDS_ONH RDSON of high-side FET to gate driver VGD/(RDS_ON + total resistance to gate input of SW FET) must not be higher than 2.5A 1.4 Ω
RDS_ONL RDSON of low-side FET to gate driver VGD/(RDS_ON + total resistance to gate input of SW FET) must not be higher than 2.5A 0.75 Ω
tSTARTUP Start-up time Delay from beginning of boost Soft-start to when LED drivers can begin 50 ms
TON Minimum switch on-time 150 ns
TOFF Minimum switch off time 150 ns
(1) This specification is not ensured by ATE