JAJSJN5B december   2020  – june 2023 LMK1D1204 , LMK1D1208

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Electrical Characteristics
    5. 7.5 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail-Safe Input and Hysteresis
      2. 9.3.2 Input Mux
    4. 9.4 Device Functional Modes
      1. 9.4.1 LVDS Output Termination
      2. 9.4.2 Input Termination
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information

6 Pin Configuration and Functions

GUID-20201103-CA0I-1TVF-WPKQ-PDW7JZ1SR3TF-low.gif Figure 6-1 LMK1D1204: RGT Package 16-Pin VQFN Top View
GUID-20201103-CA0I-VSLV-VVTS-VTWH8X7K1RNQ-low.gif Figure 6-2 LMK1D1208: RHD Package 28-Pin VQFN Top View
Table 6-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME LMK1D1204 LMK1D1208
DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT
IN0_P 6 9 I Primary: Differential input pair or single-ended input
IN0_N 7 10
IN1_P 3 5 I Secondary: Differential input pair or single-ended input.
IN1_N 4 6 Note that INP0, INN0 are used indistinguishably with IN0_P, IN0_N.
INPUT SELECT
IN_SEL 2 4 I Input Selection with an internal 500-kΩ pullup and 320-kΩ pulldown resistor, selects input port; (See Table 9-1)
BIAS VOLTAGE OUTPUT
VAC_REF0 8 11 O Bias voltage output for capacitive coupled inputs. If used, TI recommends using a 0.1-µF capacitor to GND on this pin.
VAC_REF1 — 7
DIFFERENTIAL CLOCK OUTPUT
OUT0_P 9 12 O Differential LVDS output pair number 0
OUT0_N 10 13
OUT1_P 11 16 O Differential LVDS output pair number 1
OUT1_N 12 17
OUT2_P 13 18 O Differential LVDS output pair number 2
OUT2_N 14 19
OUT3_P 15 20 O Differential LVDS output pair number 3
OUT3_N 16 21
OUT4_P — 22 O Differential LVDS output pair number 4
OUT4_N 23
OUT5_P — 24 O Differential LVDS output pair number 5
OUT5_N 25
OUT6_P — 26 O Differential LVDS output pair number 6
OUT6_N 27
OUT7_P — 2 O Differential LVDS output pair number 7
OUT7_N 3
SUPPLY VOLTAGE
VDD 5 8 P Device Power Supply (1.8V or 2.5V or 3.3V)
15
28
GROUND
GND 1 1 G Ground
— 14
MISC
DAP DAP DAP GND Die Attach Pad. Connect to the PCB ground plane for heat dissipation.
NC — — NC No Connection
(1) G = Ground, I = Input, O = Output, P = Power