The TPS54J061 uses D-CAP3 control mode to achieve fast load transient while maintaining ease-of-use. The D-CAP3 control mode architecture includes an internal ripple generation network enabling the use of very low-ESR output capacitors such as multi-layered ceramic capacitors (MLCC). No external current sensing network or voltage compensators are required with D-CAP3 control mode architecture. The role of the internal ripple generation network is to emulate the ripple component of the inductor current information and then combine it with the voltage feedback signal to regulate the loop. The amplitude of the ramp is determined by the R-C time-constant of the internal circuit. At different switching frequencies (f_SW), the R-C time-constant varies to maintain relatively constant amplitude of the internally generated ripple. Also, the device uses an internal circuit to cancel the dc offset caused by the injected ramp, which significantly reduces the DC offset caused by the output ripple voltage.

For any control topologies supporting no external compensation design, there is a minimum range or maximum range (or both) of the output filter it can support. The output filter used with TPS54J061 is a low-pass L-C circuit. This L-C filter has double pole that is described in Equation 3.

Equation 3.

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS54J061. The low frequency L-C double pole has a 180-degree drop in phase. At the output filter frequency, the gain rolls off at a –40 dB per decade and the phase drops rapidly. The internal ripple generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per decade and increases the phase by 90 degrees a decade above the zero frequency.

The inductor and capacitor selected for the output filter must be such that the double pole of Equation 3 is located below the internal zero so that the phase boost provided by the internal zero provides adequate phase margin to meet the loop stability requirement.

After identifying the application requirements, the output inductance must be designed so that the inductor peak-to-peak ripple current is approximately between 20% and 40% of the maximum output current. Use Table 6-2 to help locate the internal zero based on the selected switching frequency. In general, where reasonable (or smaller) output capacitance is desired, set the L-C double pole frequency below the internal zero frequency to determine the necessary output capacitance for stable operation.

If MLCC output capacitors are used, derating characteristics must be accounted for to determine the final output capacitance for the design. For example, when using an MLCC with specifications of 10-µF, X5R, and 6.3 V, the deratings by DC bias and AC bias are 80% and 50%, respectively. The effective derating is the product of these two factors, which in this case is 40% and 4 µF. Consult with capacitor manufacturers for specific characteristics of the capacitors used

For higher output voltage at or above 2 V, additional phase boost can be required for sufficient phase margin due to phase delay/loss for higher output voltage (large on-time (t_ON)) setting in a fixed-on-time topology based operation.

A feedforward capacitor placed in parallel with R_{FB_HS} is found to be very effective to boost the phase margin at loop crossover. Refer to the Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor application report for details.