JAJSKF5D September   2021  – November 2024 TPSM82864A , TPSM82866A

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Save Mode
      2. 7.3.2 Forced PWM Mode
      3. 7.3.3 Optimized Transient Performance from PWM to PSM Operation
      4. 7.3.4 Low Dropout Operation (100% Duty Cycle)
      5. 7.3.5 Soft Start
      6. 7.3.6 Switch Current Limit and HICCUP Short-Circuit Protection
      7. 7.3.7 Undervoltage Lockout
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable and Disable (EN)
      2. 7.4.2 Output Discharge
      3. 7.4.3 Power Good (PG)
      4. 7.4.4 Output Voltage and Mode Selection (VSET/MODE)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting The Output Voltage
        2. 8.2.2.2 Input and Output Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
        1. 8.4.2.1 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.4.4 Output Voltage and Mode Selection (VSET/MODE)

The TPSM8286xA family devices are configurable as either an adjustable output voltage or a fixed output voltage, depending on the needs of each individual application. This feature simplifies the logistics during mass production, as one part number offers several fixed output voltage options as well as an adjustable output voltage option. During the enable delay (tDelay), the device configuration is set by an external resistor connected to the VSET/MODE pin through an internal R2D (resistor to digital) converter. This configures the VREF input to the error amplifier (EA) to be either the VFB voltage (0.6-V typical) or the selected output voltage. Table 7-2 shows the options.

Table 7-2 Output Voltage Selection Table
RESISTOR AT VSET/MODE PIN (E96 SERIES, ±1% ACCURACY, 200 ppm/°C OR BETTER)FIXED OR ADJUSTABLE OUTPUT VOLTAGE
249 k or logic highAdjustable (through a resistive divider on the FB pin)
205 k3.30 V
162 k2.50 V
133 k1.80 V
105 k1.50 V
68.1 k1.35 V
56.2 k1.20 V
44.2 k1.10 V
36.5 k1.05 V
28.7 k1.00 V
23.7 k0.95 V
18.7 k0.90 V
15.4 k0.85 V
12.1 k0.80 V
10 k or logic lowAdjustable (through a resistive divider on the FB pin)

The R2D converter has an internal current source, which applies current through the external resistor, and an internal ADC, which reads back the resulting voltage level. Depending on the detected resistance, the output voltage is set. After this R2D conversion is finished, the current source is turned off to avoid current flowing through the external resistor. Make sure that the additional leakage current path is less than 20 nA and the capacitance is not greater than 30 pF from this pin to GND during R2D conversion, otherwise a false VOUT value is set. For more details, refer to the Benefits of a Resistor-to-Digital Converter in Ultra-Low Power Supplies White Paper. When the device is set to a fixed output voltage, the FB pin must be connected to the output directly. See Figure 7-4.

TPSM82864A TPSM82866A Fixed Output Voltage Application CircuitFigure 7-4 Fixed Output Voltage Application Circuit

After the start-up period (tStart-up), a different operation mode can be selected. When VSET/MODE is set to high, the device is in forced PWM mode. Otherwise, the VSET/MODE resistor pulls the pin low and the device operates in power save mode.