The TPS7H4010-SEP integrates an internal LDO, generating VCC voltage for control circuitry and MOSFET drivers. The VCC pin must have a 1-µF to 4.7-µF bypass capacitor placed as close as possible to the pin and properly grounded. Do not load the VCC pin or short it to ground during operation. Shorting VCC pin to ground during operation may damage the device.

The UVLO on VCC voltage, V_{CC_UVLO}, turns off the regulation when VCC voltage is too low. It prevents the TPS7H4010-SEP from operating until the VCC voltage is enough for the internal circuitry. Hysteresis on V_{CC_UVLO} prevents the part from turning off during power up if V_IN droops due to input current demands. The LDO generates VCC voltage from one of the two inputs: the supply voltage V_IN, or the BIAS input. When BIAS is tied to ground, the LDO input is V_IN. When BIAS is tied to a voltage higher than 3.3 V, the LDO input is V_BIAS. BIAS voltage must be lower than both V_IN and 18 V.

The BIAS input is designed to reduce the LDO power loss. The LDO power loss is:

The higher the difference between the input and output voltages of the LDO, the more loss occurs to supply the same LDO output current. The BIAS input provides an option to supply the LDO with a lower voltage than V_IN, to reduce the difference of the input and output voltages of the LDO and reduce power loss. For example, if the LDO current is 10 mA at a certain frequency with V_IN = 24 V and V_OUT = 5 V. The LDO loss with BIAS tied to ground is equal to 10 mA × (24 V – 3.27 V) = 207.3 mW, while the loss with BIAS tied to V_OUT is equal to 10 mA × (5 – 3.27) = 17.3 mW.

The efficiency improvement is more significant at light and mid loads because the LDO loss is a higher percentage in the total loss. The improvements is more significant with higher switching frequency because the LDO current is higher at higher switching frequency. The improvement is more significant when V_IN » V_OUT because the voltage difference is higher.

Figure 7-6 and Figure 7-7 show efficiency improvement with bias tied to V_OUT in a V_OUT = 5 V and f_SW = 2200 kHz application, in auto mode and FPWM mode, respectively.

VOUT = 5 V

fSW = 2200 kHz

Auto Mode

Figure 7-6 TPS7H4010 Efficiency Comparison With Bias = V_OUT to Bias = GND in Auto Mode

VOUT = 5 V

fSW = 2200 kHz

FPWM Mode

Figure 7-7 TPS7H4010 Efficiency Comparison With Bias = V_OUT to Bias = GND in FPWM Mode

TI recommends tying the BIAS pin to V_OUT when V_OUT is equal to or greater than 3.3 V and no greater than 18 V. Tie the BIAS pin to ground when not in use. A ceramic capacitor, C_BIAS, can be used from the BIAS pin to ground for bypassing. If V_OUT has high frequency noise or spikes during transients or fault conditions, a resistor (1 to 10 Ω) connected between V_OUT to BIAS can be used together with C_BIAS for filtering.

The VCC voltage is typically 3.27 V. When the TPS7H4010-SEP is operating in PFM mode with frequency foldback, VCC voltage is reduced to 3.1 V (typical) to further decrease the quiescent current and improve efficiency at very light loads. Figure 7-8 shows an example of VCC voltage change with mode change.

VOUT = 5 V

fSW = 500 kHz

VIN = 12 V

Figure 7-8 VCC Voltage vs Load Current

VCC voltage has an internal UVLO threshold, V_{CC_UVLO}. When VCC voltage is higher than V_{CC_UVLO} rising threshold, the device is active and in normal operation if V_EN > V_{EN_VOUT_H}. If VCC voltage droops below V_{CC_UVLO} falling threshold, the V_OUT is shut down.