JAJSKK6A November 2020 – December 2021 TPS7H4010-SEP
PRODUCTION DATA
Because VOUT = 5 V in this design, the BIAS pin is tied to VOUT to reduce LDO power loss. The output voltage is supplying the LDO current instead of the input voltage. The power saving is ILDO × (VIN – VOUT). The power saving is more significant when VIN >> VOUT and with higher frequency operation. To prevent VOUT noise and transients from coupling to BIAS, a series resistor, 1 Ω to 10 Ω, may be added between VOUT and BIAS. A bypass capacitor with a value of 1 μF or higher can be added close to the BIAS pin to filter noise.