JAJSKK6A November   2020  – December 2021 TPS7H4010-SEP

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Synchronous Step-Down Regulator
      2. 7.3.2  Auto Mode and FPWM Mode
      3. 7.3.3  Fixed-Frequency Peak Current-Mode Control
      4. 7.3.4  Adjustable Output Voltage
      5. 7.3.5  Enable and UVLO
      6. 7.3.6  Internal LDO, VCC_UVLO, and BIAS Input
      7. 7.3.7  Soft Start and Voltage Tracking
      8. 7.3.8  Adjustable Switching Frequency
      9. 7.3.9  Frequency Synchronization and Mode Setting
      10. 7.3.10 Internal Compensation and CFF
      11. 7.3.11 Bootstrap Capacitor and VBOOT-UVLO
      12. 7.3.12 Power-Good and Overvoltage Protection
      13. 7.3.13 Overcurrent and Short-Circuit Protection
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 DCM Mode
        3. 7.4.3.3 PFM Mode
        4. 7.4.3.4 Fault Protection Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Output Voltage Setpoint
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Input Capacitors
        4. 8.2.2.4  Inductor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  Feed-Forward Capacitor
        7. 8.2.2.7  Bootstrap Capacitors
        8. 8.2.2.8  VCC Capacitor
        9. 8.2.2.9  BIAS
        10. 8.2.2.10 Soft Start
        11. 8.2.2.11 Undervoltage Lockout Setpoint
        12. 8.2.2.12 PGOOD
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout For EMI Reduction
      2. 10.1.2 Ground Plane
      3. 10.1.3 Optimize Thermal Performance
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –55°C to +125°C, unless otherwise stated.  Minimum and maximum limits are specified through test, design, or statistical correlation.  Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.  Unless otherwise stated, VIN = 12 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (PVIN PINS)
PVIN Operating input voltage 3.5 32 V
ISD Shutdown quiescent current; measured at PVIN pin(1) VEN = AGND, TJ = 25°C 0.8 10 µA
IQ_NONSW Operating quiescent current from PVIN (non-switching) VEN = 2 V, VFB = 1.5 V, VBIAS = 3.3 V external 0.6 12 µA
ENABLE (EN PIN)
VEN_VCC_H Enable input high level for VCC output VEN rising 1.15 V
VEN_VCC_L Enable input low level for VCC output VEN falling 0.3 V
VEN_VOUT_H Enable input high level for VOUT VEN rising 1.14 1.196 1.25 V
VEN_VOUT_HYS Enable input hysteresis for VOUT VEN falling hysteresis 100 mV
ILKG_EN Enable input leakage current VEN = 2 V 1.4 200 nA
INTERNAL LDO (VCC PIN, BIAS PIN)
VCC Internal VCC voltage PWM operation 3.27 V
PFM operation 3.1
VCC_UVLO Internal VCC undervoltage lockout VCC rising 2.96 3.14 3.27 V
VCC falling hysteresis 605 mV
VBIAS_ON Input changeover VBIAS rising 3.09 3.25 V
VBIAS falling hysteresis 63 mV
IBIAS_NONSW Operating quiescent current from external VBIAS (non-switching) VEN = 2 V, VFB = 1.5 V, VBIAS = 3.3 V external 21 50 µA
VOLTAGE REFERENCE (FB PIN)
VFB Feedback voltage PWM mode 0.987 1.006 1.017 V
ILKG_FB Input leakage current at FB pin VFB = 1 V 0.2 60 nA
HIGH SIDE DRIVER (CBOOT PIN)
VCBOOT_UVLO CBOOT - SW undervoltage lockout 1.6 2.2 2.7 V
CURRENT LIMITS AND HICCUP
IHS_LIMIT Short-circuit, high-side current limit(2) 7.4 8.7 9.85 A
ILS_LIMIT Low-side current limit(2) 5.8 6.6 7.25 A
INEG_LIMIT Negative current limit –5 A
VHICCUP Hiccup threshold on FB pin 0.36 0.4 0.44 V
IL_ZC Zero cross-current limit –0.05 A
SOFT START (SS/TRK PIN)
ISSC Soft-start charge current 1.8 2 2.2 µA
RSSD Soft-start discharge resistance UVLO, TSD, OCP, or EN = AGND 1 kΩ
POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION
VPGOOD_OV Power-good overvoltage threshold % of FB voltage 106% 110% 113%
VPGOOD_UV Power-good undervoltage threshold % of FB voltage 86% 90% 93%
VPGOOD_HYS Power-good hysteresis % of FB voltage 1.2%
VPGOOD_VALID Minimum input voltage for proper PGOOD function 50-µA pullup to PGOOD pin, VEN = AGND, TJ = 25℃ 1.3 2 V
RPGOOD Power-good ON-resistance VEN = 2.5 V 40 100 Ω
VEN = AGND 30 90
MOSFETS
RDS_ON_HS(3) High-side MOSFET ON-resistance IOUT = 1 A, VBIAS = VOUT = 3.3 V 53 90 mΩ
RDS_ON_LS(3) Low-side MOSFET ON-resistance IOUT = 1 A, VBIAS = VOUT = 3.3 V 31 55 mΩ
THERMAL SHUTDOWN
TSD(4) Thermal shutdown threshold Shutdown threshold 160 °C
Recovery threshold 135
(1) Shutdown current includes leakage current of the switching transistors.
(2) This current limit was measured as the internal comparator trip point. Due to inherent delays in the current limit comparator and drivers, the peak current limit measured in closed loop with faster slew rate will be larger, and valley current limit will be lower.
(3) Measured at pins.
(4) Ensured by design.