JAJSKN2B November   2020  – September 2021 TPS25864-Q1 , TPS25865-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Power-Down or Undervoltage Lockout
      2. 10.3.2  Input Overvoltage Protection (OVP) - Continuously Monitored
      3. 10.3.3  Buck Converter
      4. 10.3.4  FREQ/SYNC
      5. 10.3.5  Bootstrap Voltage (BOOT)
      6. 10.3.6  Minimum ON-Time, Minimum OFF-Time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Selectable Output Voltage (VSET)
      9. 10.3.9  Current Limit and Short Circuit Protection
        1. 10.3.9.1 USB Switch Current Limit
        2. 10.3.9.2 Interlocking for Two-Level USB Switch Current Limit
        3. 10.3.9.3 Cycle-by-Cycle Buck Current Limit
        4. 10.3.9.4 OUT Current Limit
      10. 10.3.10 Cable Compensation
      11. 10.3.11 Thermal Management With Temperature Sensing (TS) and OTSD
      12. 10.3.12 Thermal Shutdown
      13. 10.3.13 USB Specification Overview
      14. 10.3.14 USB Port Operating Modes
        1. 10.3.14.1 Dedicated Charging Port (DCP) Mode
          1. 10.3.14.1.1 DCP BC1.2 and YD/T 1591-2009
          2. 10.3.14.1.2 DCP Divider-Charging Scheme
          3. 10.3.14.1.3 DCP 1.2-V Charging Scheme
        2. 10.3.14.2 DCP Auto Mode
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Active Mode
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Output Voltage Setting
        2. 11.2.2.2 Switching Frequency
        3. 11.2.2.3 Inductor Selection
        4. 11.2.2.4 Output Capacitor Selection
        5. 11.2.2.5 Input Capacitor Selection
        6. 11.2.2.6 Bootstrap Capacitor Selection
        7. 11.2.2.7 Undervoltage Lockout Set-Point
        8. 11.2.2.8 Cable Compensation Set-Point
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
    3. 13.3 Ground Plane and Thermal Considerations
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 サポート・リソース
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

7 Pin Configuration and Functions

GUID-20201105-CA0I-XMFZ-WPGW-K3JVK1GNXRVV-low.gif Figure 7-1 TPS2586x-Q1 RPQ Package25-Pin (QFN)Top View
Table 7-1 Pin Functions for TPS2586x-Q1 RPQ Package
PIN TYPE (1) DESCRIPTION
NAME NO.
VSET 1 A Output Voltage Setting. Short to GND to set the 5.17-V output voltage. Float or pull up to VSENSE to set 5.1-V output voltage. Tie to GND through a 40.2-KΩ resistor to set 5.3-V output voltage. Tie to GND through a 80.6-KΩ resistor to set 5.4-V output voltage.
TS 2 A Temperature Sense terminal. Connect the TS input to the NTC thermistor.
BIAS 3 P Input of internal bias supply. Must connect to the SENSE pin directly. Power the internal circuit.
PA_DP 4 A D+ data line. Connect to USB Port A connector.
PA_DM 5 A D- data line. Connect to USB Port A connector.
AGND 6 P Analog ground terminal. Connect AGND to PGND.
CFG1 7 A Configuration pin. For internal circuit, must connect a 5.1-KΩ resistor to AGND.
NC 8, 14 A Makes no electrical connection.
CFG2 9 A Configuration pin. For internal circuit, must connect a 11.8-KΩ resistor to AGND.
PA_BUS 10 P Port A BUS output.
SENSE 11 P Output Voltage Sensing. External load on this pin is strictly prohibited. Connect to the other side of the external inductor.
PB_BUS 12 P Port B BUS output.
OUT 13 P Output pin. Provide 5.1-V voltage to power external load with maximum 200-mA capability. The voltage follows the VSET setting.
CFG3 15 A Configuration pin. For internal circuit, must connect a 5.1-KΩ resistor to AGND.
PGND 16, 24, 25 P Power Ground terminal. Connected to the source of LS FET internally. Connect to system ground, AGND, and the ground side of the CIN and COUT capacitors. The path to CIN must be as short as possible.
PB_DM 17 A D- data line. Connect to USB port B connector.
PB_DP 18 A D+ data line. Connect to USB port B connector.
FREQ/ SYNC 19 A Switching Frequency Program and External Clock Input. Connect a resistor from FREQ to GND to set the switching frequency.
EN/UV 20 A Enable pin. Precision enable controls the regulator switching action. Do not float. High = on, Low = off. Can be tied to SENSE directly. Precision enable input allows adjustable UVLO by external resistor divider if tie to IN pin.
BOOT 21 P Bootstrap capacitor connection. Internally, the BOOT is connected to the cathode of the boost-strap diode. Connect the 0.1-μF bootstrap capacitor from SW to BOOT.
IN 22 P Input power. Connected to external DC supply. Expected range of bypass capacitors is 1 μF to 10 μF, connect from IN to PGND. Can withstand up to 36 V without damage but operating is suspended if VIN is above the 26-V OVP threshold.
SW 23 P Switching output of the regulator. Internally connected to source of the HS FET and drain of the LS FET. Connect to output inductor.
(1) A = Analog, P = Power, G = Ground.