JAJSKN2B November 2020 – September 2021 TPS25864-Q1 , TPS25865-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY VOLTAGE (IN PIN) | ||||||
ISD | Shutdown quiescent current; measured at IN pin. | VEN/UV = 0, -40℃ ≤ TJ ≤ 85℃ | 34 | 63 | uA | |
IQ | Operating quiescent current (DCDC disable) | VEN = VSENSE, CFG1&CFG3 = open, -40℃ ≤ TJ ≤ 85℃ | 200 | µA | ||
VOVLO_R | Voltage on VIN pin when buck regulator stops switching | 26.6 | 27.5 | 28.4 | V | |
VOVLO_HYS | Hysteresis | 0.5 | V | |||
ENABLE AND UVLO (EN/UVLO PIN) | ||||||
VEN/UVLO_R | Rising threshold for not in External UVLO | VEN/UV rising threshold | 1.26 | 1.3 | 1.34 | V |
VEN/UVLO_HYS | Hysteresis | VEN/UVLO falling | 100 | mV | ||
BOOTSTRAP | ||||||
VBTST_UVLO | Bootstrap voltage UVLO threshold | 2.2 | V | |||
RBOOT | Bootstrap pull-up resistence | VSENSE - BOOT = 0.1 V | 7.7 | Ω | ||
BUCK REGULATOR | ||||||
IL-SC-HS | High-side current limit | BOOT - SW = 5 V | 10.2 | 11.4 | 12.6 | A |
IL-SC-LS | Low-side current limit | SENSE = 5 V | 8.5 | 10 | 11.5 | A |
IL-NEG-LS | Low-side negative current limit | SENSE = 5 V | -7 | -5 | -3 | A |
IZC | Zero current detector threshold | 0.01 | A | |||
VSENSE | BUCK Output voltage | CFG1 or CFG3 pulldown resistance = 5.1KΩ, VSET float or pull up to VSENSE, TJ = 25℃ | -1% | 5.1 | +1% | V |
CFG1 or CFG3 pulldown resistance = 5.1KΩ, VSET short to AGND, TJ = 25℃ | -1% | 5.17 | +1% | V | ||
CFG1 or CFG3 pulldown resistance = 5.1KΩ, RVSET = 40.2KΩ, TJ = 25℃ | -1% | 5.3 | +1% | V | ||
CFG1 or CFG3 pulldown resistance = 5.1KΩ, RVSET = 80.6KΩ, TJ = 25℃ | -1% | 5.4 | +1% | V | ||
VSENSE | BUCK Output voltage accuracy | CFG1 or CFG3 pulldown resistance = Rd, -40℃ ≤ TJ ≤ 150℃ | –2 | 2 | % | |
VDCDC_UVLO_R | SENSE input level to enable DCDC switching | VSENSE rising, CFG1 or CFG3 pull down resistance = 5.1KΩ | 3.85 | 4 | 4.15 | V |
VDCDC_UVLO_HYS | Hysteresis | VSENSE falling, CFG1 or CFG3 pull down resistance = 5.1KΩ | 0.4 | V | ||
VDROP | Dropout voltage ( VIN-VSENSE ) | VIN = VSENSE + VDROP, VSENS = 5.1 V, IPA_BUS = 2.4A, IPB_BUS = 2.4A | 300 | mV | ||
RDS-ON-HS | High-side MOSFET ON-resistance | IPA_BUS = 2.4 A, IPB_BUS = 2.4 A, BOOT - SW = 5 V, -40℃≤ TJ ≤ 150℃ | 18 | 34 | mΩ | |
RDS-ON-LS | Low-side MOSFET ON-resistance | IPA_BUS = 2.4 A, IPB_BUS = 2.4 A, VSENSE = 5 V, -40℃ ≤ TJ ≤150℃ | 9.5 | 18.5 | mΩ | |
POWER SWITCH AND CURRENT LIMIT | ||||||
RDS-ON_USB | USB Load Switch MOSFET ON-resistance | IPA_BUS = 2.4 A, IPB_BUS = 2.4 A; -40℃ ≤ TJ ≤ 150℃ | 6.8 | 11.73 | mΩ | |
RDS-ON_OUT | OUT Load Switch MOSFET ON-resistance | IOUT = 0.3 A | 230 | mΩ | ||
VUSBLS_UVLO_R | Voltage on SENSE pin that will enable the USB Load Switch | 3.95 | 4.1 | 4.25 | V | |
VUSBLS_UVLO_HYS | Hysteresis | 200 | mV | |||
IOS_HI | BUS output short-circuit secondary current limit | 3938 | 4376 | 4814 | mA | |
TJ = 25℃ | 4157 | 4376 | 4595 | mA | ||
IOS_BUS | BUS output short-circuit current limit | 2461 | 2735 | 3009 | mA | |
TJ = 25℃ | 2598 | 2735 | 2872 | mA | ||
IOS_OUT | OUT output short-circuit current limit | Short circuit current limit | 390 | 450 | 495 | mA |
CABLE COMPENSATION VOLTAGE | ||||||
VDROP_COM | Cable compensation voltage | IPA_BUS or IPB_BUS = 2.4A, VSET= GND (set 5.17V output) | 70 | 90 | 110 | mV |
BC 1.2 DOWNSTREAM CHARGING PORT | ||||||
RDPM_SHORT | DP and DM shorting resistance | 70 | 200 | Ω | ||
DIVIDER 3 MODE | ||||||
VDP_DIV3 | DP output voltage | 2.57 | 2.7 | 2.84 | V | |
VDM_DIV3 | DM output voltage | 2.57 | 2.7 | 2.84 | V | |
RDP_DIV3 | DP output impedance | IDP_IN = –5 µA | 24 | 30 | 36 | kΩ |
RDM_DIV3 | DM output impedance | IDM_IN = –5 µA | 24 | 30 | 36 | kΩ |
1.2-V MODE | ||||||
VDP_1.2V | DP output voltage | 1.12 | 1.2 | 1.26 | V | |
VDM_1.2V | DM output voltage | 1.12 | 1.2 | 1.26 | V | |
RDP_1.2V | DP output impedance | IDP_IN = –5 µA | 84 | 100 | 126 | kΩ |
RDM_1.2V | DM output impedance | IDM_IN = –5 µA | 84 | 100 | 126 | kΩ |
FREQ/SYNC THRESHOLD | ||||||
VIH_FREQ/SYNC | FREQ/SYNC high threshold for external clock synchronization | Amplitude of SYNC clock AC signal (measured at FREQ/SYNC pin) | 2 | V | ||
VIL_FREQ/SYNC | FREQ/SYNC low threshold for external clock synchronization | Amplitude of SYNC clock AC signal (measured at FREQ/SYNC pin) | 0.8 | V | ||
TEMPERATURE SENSING | ||||||
VWARN_HIGH | Temperature warning threshold rising | As percentage to VSENSE | 0.475 | 0.5 | 0.525 | V/V |
VWARN_HYS | Hysteresis | As percentage to VSENSE | 0.1 | V/V | ||
VHOT_HIGH | Temperature Hot assert threshold rising to reduce SENS voltage | As percentage to VSENSE | 0.618 | 0.65 | 0.683 | V/V |
VHOT_HYS | Hysteresis | As percentage to VSENSE | 0.1 | V/V | ||
VR_VSENS | VSENSE voltage decay when Temperature Hot assert | TS pin voltage rise above 0.65 * VSENSE | 4.77 | V | ||
THERMAL SHUTDOWN | ||||||
TLS_SD | USB Load Switch Over Temperature | Shutdown threshold | 160 | °C | ||
Recovery threshold | 150 | °C | ||||
TSD | Thermal shutdown | Shutdown threshold | 166 | °C | ||
Recovery threshold | 154 | °C |