In addition to the gain calibration, the phase delay in each channel can be finely calibrated or adjusted in steps of one modulator clock cycle for a cycle range of 0 to 255 for the phase error. Phase calibration clock is dependent on PDM clock used. For a PDM_CLK of 6.144 MHz (the output data sample rate is multiples or submultiples of 48 kHz) or 5.6448 MHz (the output data sample rate is multiples or submultiples of 44.1 kHz), the phase calibration clock is the same as the PDM_CLK. For a PDM_CLK equal to or lower than 3.072 MHz (the output data sample rate is multiples or submultiples of 48 kHz), the phase calibration clock used is 3.072 MHz. Similarly, for a PDM_CLK of 2.8224 MHz, 1.4112 MHz, or 705.6 kHz (the output data sample rate is multiples or submultiples of 44.1 kHz), the phase calibration clock used is 2.8224MHz. This feature is very useful for many applications that must match the phase with fine resolution between each channel, including any phase mismatch across channels resulting from external components or microphones. Table 7-12 shows the available programmable options for channel phase calibration for a digital microphone with a PDM_CLK of 6.144 MHz or 5.6448 MHz.

For a digital microphone interface with a PDM_CLK frequency below 3.072 MHz, the phase calibration range is from 0 to 127 of the phase calibration clock (3.072 MHz for the output data sample rate is multiples or submultiples of 48 kHz and 2.8224 MHz for the output data sample rate is multiples or submultiples of 44.1 kHz). The phase calibration for a PDM_CLK frequency below 3.072 MHz can be configured using the CH1_PCAL[7:1] register bits for channel 1.

Similarly, the channel phase calibration setting for input channel 2 to channel 4 can be configured using the CH2_PCAL (P0_R69) to CH4_PCAL (P0_R79) register bits, respectively.